search for: msix_enable_mask

Displaying 14 results from an estimated 14 matches for "msix_enable_mask".

2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 05
1
[PATCHv3 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 02
0
[PATCHv2 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 18
0
[PATCHv5 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 10
0
[PATCHv4 05/13] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 May 25
1
[PATCH 05/11] qemu: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2009 Jun 21
1
[PATCHv6 05/12] qemu/pci: MSI-X support functions
...LE (1 << 15) +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) + +/* MSI-X capability structure */ +#define MSIX_TABLE_OFFSET 4 +#define MSIX_PBA_OFFSET 8 +#define MSIX_CAP_LENGTH 12 + +/* MSI enable bit is in byte 1 in FLAGS register */ +#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) + +/* MSI-X table format */ +#define MSIX_MSG_ADDR 0 +#define MSIX_MSG_UPPER_ADDR 4 +#define MSIX_MSG_DATA 8 +#define MSIX_VECTOR_CTRL 12 +#define MSIX_ENTRY_SIZE 16 +#define MSIX_VECTOR_MASK 0x1 + +/* How much space does an MSIX table need. */ +/* The spec requir...
2015 May 12
0
KVM VHOST-BLK is not working
...SIX config options. I am seeing a failure in the QEMU function msix_enabled during the initialization of the block device While the first expression (dev->cap_present & QEMU_PCI_CAP_MSIX) is successful, the second one (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_ENABLE_MASK) is failing. I could not see a msix_init function from hw/block/virtio-blk.c whereas there is one for VHOST-NET from vmxnet3_init_msix. I will appreciate if someone could point out what I am missing here. Thanks and Regards Sudheer -------------- next part -------------- An HTML attachment was...
2015 May 12
0
KVM VHOST-BLK is not working
...SIX config options. I am seeing a failure in the QEMU function msix_enabled during the initialization of the block device While the first expression (dev->cap_present & QEMU_PCI_CAP_MSIX) is successful, the second one (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_ENABLE_MASK) is failing. I could not see a msix_init function from hw/block/virtio-blk.c whereas there is one for VHOST-NET from vmxnet3_init_msix. I will appreciate if someone could point out what I am missing here. Thanks and Regards Sudheer -------------- next part -------------- An HTML attachment was...