search for: mrmsrcreg

...defined in lib/Target/X86/X86InstrArithmetic.td. we only have TEST defined with F6 & other opcode like below. any hint please? thanks. let isCompare = 1 in { let Defs = [EFLAGS] in { let isCommutable = 1 in { def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>; def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>; def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>; def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>; } // isCommutable...

...this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp) def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (!SOME_CONCAT("x86f", OpNode) FR32: $src1, FR32:$src2))]>; // Vector operation def PSrr : PSI<o...

...rc1|$src1, $src2}", > [(set GR32:$dst, > - (int_x86_sse42_crc32_8 GR32:$src1, > + (int_x86_sse42_crc32_32_8 GR32:$src1, > (load addr:$src2)))]>; > - def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst), > + def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst), > (ins GR32:$src1, GR8:$src2), > "crc32{b} \t{$src2, $src1|$src1, $src2}", > [(set GR32:$dst, > -...

...sn't use movd). Also, notice that the last two instructions above should ideally just be a single movd to memory, instead of first writing to a GP register. In the same breath, I believe the encoding of MMX_MOVDQ2Qrr is incorrect. I've been able to fix the first two definitions by using MRMSrcReg (and set hasNoSideEffects). I'm not sure about the third definition though, is this for 3DNow! And should it use MRMSrcReg as well? Thanks, Nicolas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachment...

...LTIN(__builtin_x86_max_qb, "iii", "") I define the intrinsic as Pseudo instruction,it succeed. But when mapping a new instruction.I don't know how to do. In x86InstrArithmetic.td. I add ,(To make sure the Sched is right, I use the WriteIMul16Reg ) def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2}", [(set GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ; when compile LLVM , the error appears. "[ 97%] Updating X86GenAsmWriter1.inc... Unhandled immediate en...

...ple on me? :) -Chris > > > (WARNING! Hacked-up tablegen ahead!) > > multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, > SDNode OpNode> { > // Vector operation emulating scalar (fp) > def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, > FR32: > $src2), > !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, > $src2}"), > [(set FR32:$dst, (!SOME_CONCAT("x86f", OpNode) > FR32: > $src1, FR32:$src2))]>; >...

...mal code on x86-64 is due to a missing dagcombine; it doesn't know that extracting an i64 and truncating it to an i32 is equivalent to extracting an i32. > In the same breath, I believe the encoding of MMX_MOVDQ2Qrr is incorrect. > I’ve been able to fix the first two definitions by using MRMSrcReg (and set > hasNoSideEffects). I’m not sure about the third definition though, is this > for 3DNow! And should it use MRMSrcReg as well? Also fixed in r75142. Note that MMX_MOVQ2FR64rr is actually exactly the same instruction as MMX_MOVQ2DQrr; they're separated because it's a bit mor...

...class sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, > Operand CC, Intrinsic Int, string asm, > string asm_alt, Domain d, > OpndItins itins = SSE_ALU_F32P> { > def rri : PIi8<0xC2, MRMSrcReg, > (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, > [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], > itins.rr, d>, > Sched<[WriteFAdd]>; > def rmi : PIi8<0xC2, MRMSrcMem, > (outs RC:$dst), (...

...Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem, Commutative]>; Untested multiclass! Look for SOME_CONCAT. multiclass myintrinsics<bits<8> opc, string OpcodeStr, Intrinsic Intr> { // Scalar intrinsics def SSrr_Int SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (SOME_CONCAT(Intr, _ss) FR32:$src1, FR32: $src2))]> { def SDrr_Int SSI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, F...

hi, some instructions mismatch between assembler & disassembler, like below. it seems this happens with all SSECC related instructions? thanks, Jun $ echo "cmpps xmm1, xmm2, 23" | ./Release+Asserts/bin/llvm-mc -assemble -triple=x86_64 --output-asm-variant=1 -x86-asm-syntax=intel -show-encoding .text cmpps xmm1, xmm2, 23 # encoding: [0x0f,0xc2,0xca,0x17] $

...d). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set RC:$dst, (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))...

Hi all, I'm trying to simulate an extended x86 architecture on gem5 with several new instructions. My hardware setup is done and now I'd like llvm to accept the existence of the new instruction passed in inline assembly and output the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and I would like the instruction to have the same operands and return values as CVTPS2PI

...ry file. I guess, the schedule of an instruction tells the machine how to do . I don't konw if it's right. For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are her...

...ensure that dst and src2 are the same register? I see that the assembly/disassembly string assumes this is the case. Also, it uses i64:$src which is an i64 and not a GPR. What is the distinction there? X86 does this differently. src1 and src2 are GR64 registers. def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "imul{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, EFLAGS, (X86smul_flag GR64:$src1, GR64:$src2))]>, Sched<[WriteIMul...

...onstraints = "$src1 = $dst" in { multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int, bit Commutable = 0> { // Scalar operation, reg+reg. def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2), !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> { let isCommutable = Commutable; } // Scalar operati...

...se X86ISD::max_qb: return "X86ISD::max_qb"; In /lib/Target/X86/X86InstrInfo.td: def X86max_qb_flag : SDNode<"X86ISD::max_qb", SDTBinaryArithWithFlags, [SDNPCommutative]>; In /lib/Target/X86/X86InstrArithmetic.td: def max_qb : I<0xff,MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), "max_qb\t {$dst, $src1,$src2|$src1,$src2, $dst}", [(set GR32:$dst,EFLAGS,(X86max_qb_flag GR32:$src1, GR32:$src2))]>, Sched<[WriteIMul]>, TB, OpSize32 ; I think it can be work ,at least work as one multip...

...ry file. I guess, the schedule of an instruction tells the machine how to do . I don't konw if it's right. For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication. def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul32Reg]>, TB, OpSize32; And in X86ScheduleXXX.td ,there is definition of Ports and so on. My questions are her...

0x0f 0x6f 0xc8 And 0x0f 0x7f 0xc1 Should both be movq % mm0, % mm1. (AT&T) However, llvm 3.4 at least does not recognise the second variant as being a valid instruction. We are currently compiling up latest src incase it has been fixed. If not, could someone take a look or recommend how to fix? Lee -------------- next part -------------- An HTML attachment was scrubbed... URL:

...- modrm.mod!=0x3, with a fixed value(0-7) in modrm[5:3]. modrm[2:0] and optional sib byte and displacement encode memory address. MRMDestReg - modrm.mod==0x3, modrm[2:0] encodes destination register. if vex.vvvv is used encodes the next register, mrm[5:3] encodes the second or third register. MRMSrcReg - modrm.mod==0x3, modrm[5:3] encodes destination register. if vex.vvvv is used encodes the next register, mrm[2:0] encodes the second or third register. MRMSrcReg4VOp3 - like MRMSrcReg, but vex.vvvv and memory operand are swapped. Rarely used MRMSrcRegOp4 - like MRMSrcReg, but a second sou...

...quot;$src1 = $dst" in { > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > SDPatternOperator OpNode = null_frag> { > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > (ins RC:$src1, RC:$src2, RC:$src3), > !strconcat(OpcodeStr, > "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), > [(set RC:$dst, > (OpVT (OpNode RC:$sr...