search for: mrm4r

...that ATT syntax states that it should be referenced as "%cl" while Intel says just "cl" but these references occur in X86InstInfo.td and this means that it is shared between Intel and ATT printing! For example, the shift rules: let Uses = [CL] in { def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), "shl{b}\t{%cl, $dst|$dst, %CL}", [(set GR8:$dst, (shl GR8:$src, %CL))]>; def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), "shl{w}\t{%cl, $dst|$dst, %CL}",...

Hi, I'm trying to revive jacobly0's Z80 back-end (from https://github.com/jacobly0/llvm-z80) and build it with a current version of LLVM. Apart from some interface changes, I'm stuck at building the tables. Specifically, the generation of the DAG instruction selector causes an assertion in the table generator: Assertion failed: Ops.size() >= NumSrcResults &&

...::saveCalleeSavedRegisters to detect that there is a tail called function that uses a callee saved register and move it to another (EAX). that's how the TAILJMP instruction looks: let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL jmpr", []>; btw. i am currently working with llvm-2.0 codebase. thanks for any help regards arnold

...ter to (right before the callee saved register restore) but thinking a little further that's nonsense. something like let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1, ifDestRegisterisCalleeSavedEmitAMoveToECXAndJumpToThat=1 in def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL jmpr", []>; On 8 Aug 2007, at 18:27, Dale Johannesen wrote: > Inserting a pseudo before your tail call that defines all the callee- > saved > registers should work. See FP_REG_KILL. the trick of dale seems to w...

Hello, Arnold. > Is there a way to indicate that the register the tail call > instruction uses as destination needs to be valid after the callee > saved registers have been restored? (some X86InstrInfo.td foo magic > maybe ?) It's wrong way to do the things. Because in this case you either violate the ABI for callee, or you're restricted to do tail call lowering only for

...aved register restore) but thinking a little > further that's nonsense. > > something like > let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, > noResults = 1, > ifDestRegisterisCalleeSavedEmitAMoveToECXAndJumpToThat=1 > in > def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # > TAIL CALL jmpr", > []>; > > On 8 Aug 2007, at 18:27, Dale Johannesen wrote: >> Inserting a pseudo before your tail call that defines all the callee- >> saved >> registers should work. See FP_REG_KILL. &...

...quot;static"? let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL", + []>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*} $dst # TAILCALL", + []>; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp\t{*}$dst # TAIL CALL", []>; Pleas...

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...CurOp+1, IsPIC, Is64BitMode); > + CurOp += 5; > + if (CurOp != NumOps) > + FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); > + break; > + } > + > + case X86II::MRM0r: case X86II::MRM1r: > + case X86II::MRM2r: case X86II::MRM3r: > + case X86II::MRM4r: case X86II::MRM5r: > + case X86II::MRM6r: case X86II::MRM7r: > + ++FinalSize; > + FinalSize += sizeRegModRMByte(); > + > + if (CurOp != NumOps) { > + const MachineOperand &MO1 = MI.getOperand(CurOp++); > + unsigned Size = X86InstrInfo::sizeOfImm(Desc);...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And