search for: mregisterinfo

...pass requires LiveIntervals to build the interference graph, Ok. > because LiveVariables do not provide an interface to iterate through > all viritual registers. Ok, you could add a method to LiveVariables that returns VirtRegInfo.size(). The virtual registers are defined by the range: [MRegisterInfo::FirstVirtualRegister, MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] Alternatively, the same information can be obtained from the SSARegMap for the function: given a MachineFunction, use something like: NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1; These also start from MRegi...

One of my pass requires LiveIntervals to build the interference graph, because LiveVariables do not provide an interface to iterate through all viritual registers. But LiveIntervalAnalysis.h is not in "include/llvm/CodeGen", so I have to either include it by: #include "../../llvm/lib/CodeGen/LiveIntervalAnalysis.h" or point my project include path to

...ner <sabre at nondot.org> wrote: > > because LiveVariables do not provide an interface to iterate through > > all viritual registers. > > Ok, you could add a method to LiveVariables that returns > VirtRegInfo.size(). The virtual registers are defined by the range: > [MRegisterInfo::FirstVirtualRegister, > MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] > > Alternatively, the same information can be obtained from the SSARegMap for > the function: given a MachineFunction, use something like: > > NumVRegs = MF.getSSARegMap()->getLastVirtReg()+1;...

Hi, right now, LLVM does register spilling by: 1. Creating stack object 2. Passing index of that stack object to MRegisterInfo::storeRegToStackSlot 3. At later stage, frame indices are replaced by calling to MRegisterInfo::eliminateFrameIndex. This works for me, but there's slight problem. The target does not have "register + contant" addressing mode, so accessing frame index should be done like this: so...

Hey, guys, I am creating some move instructions with MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction that I just created? Is there a way to do something like: // mbb is MachineBasicBlock, reg_info is MRegisterInfo MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); iter--; (??...

Hi, in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' parameter, that is not documented. Can somebody explain what does it mean? Thanks, Volodya

On Sat, 13 May 2006, Vladimir Prus wrote: > in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' > parameter, that is not documented. > > Can somebody explain what does it mean? Basically, it gives the target more information about the spill. In particular, it specifies the register class to use for the copy. The target can choose to ignore this if it

...definitely does run on machine code. I was thinking that it only transformed instructions with virtual registers because of this code in the TwoAddressInstructionPass.cpp: unsigned regA = mi->getOperand(0).getReg(); unsigned regB = mi->getOperand(1).getReg(); assert(MRegisterInfo::isVirtualRegister(regA) && MRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); By machine code I meant code with virtual registers, instead of machine (physical) registers; not the passes on machine...

The docs for the above-mentioned function say: This method may modify or replace the specified instruction, as long as it keeps the iterator pointing the the finished product. What does it mean to "keep an interator". Was "invalidates the iterator" intended, so something else. Another question, is how do I really replace the instruction. The operator= is private

Chris Lattner wrote: > On Sat, 13 May 2006, Vladimir Prus wrote: >> in LLVM CVS the afore-mentioned function has 'const TargetRegisterClass*' >> parameter, that is not documented. >> >> Can somebody explain what does it mean? > > Basically, it gives the target more information about the spill. In > particular, it specifies the register class to use

...ot.org> wrote: >>> because LiveVariables do not provide an interface to iterate through >>> all viritual registers. >> >> Ok, you could add a method to LiveVariables that returns >> VirtRegInfo.size(). The virtual registers are defined by the range: >> [MRegisterInfo::FirstVirtualRegister, >> MRegisterInfo::FirstVirtualRegister+VirtRegInfo.size()] >> >> Alternatively, the same information can be obtained from the SSARegMap for >> the function: given a MachineFunction, use something like: >> >> NumVRegs = MF.getSSARegMap()-&...

On 08/09/05, Chris Lattner <sabre at nondot.org> wrote: > This code isn't actually replacing the virtual register with a physreg. Then why changing its optype? It makes the assertion fails: MachineOperand& MO = inst.getOperand(n); if (MRegisterInfo::isVirtualRegister(MO.getReg())) { assert(MachineOperand::MO_VirtualRegister == MO.getType()); ... } Is that alright? Some of my code using MachineOperand::getType() instead of MRegisterInfo::is{Physical,Virtual}Register() to check the register type. -- Tzu-Chien Chiu, 3D Graphics Hardware...

...() always insert the move instruction before "iter". Just use prior(iter) after the insertion to reference the newly created move instruction. Evan On Feb 21, 2007, at 11:17 PM, Fernando Magno Quintao Pereira wrote: > > Hey, guys, I am creating some move instructions with > MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction > that I just created? Is there a way to do something like: > > // mbb is MachineBasicBlock, reg_info is MRegisterInfo > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > reg_info->copyRegToReg(mbb, it...

...dded the "-regalloc=linearscan" to provoke > the error). Yes, that's exactly what I meant... thanks for reading my mind! :) It looks like this is where things start to go downhill (LiveIntervals.cpp:559): LiveIntervals::Interval::Interval(unsigned r) : reg(r), weight((MRegisterInfo::isPhysicalRegister(r) ? std::numeric_limits<float>::infinity() : 0.0F)) { For a physical register (EDX in this case) it appears that the interval is being created, but gets a 0 weight instead of an infinity weight. This implies that the MRegisterInfo::isPhysicalRegister migh...

...mpute spill // weights, coalesce virtual registers and remove identity moves ... for (unsigned i = 0; i < mii->getNumOperands(); ++i) { const MachineOperand& mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && MRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned reg = rep(mop.getReg()); mii->SetMachineOperandReg(i, reg); LiveInterval &RegInt = getInterval(reg); RegInt.weight += (mop....

On Wed, Apr 21, 2004 at 11:01:48AM +0200, Finn S Andersen wrote: > For some of the benchmarks the linear scan regalloc > works. When it does, results are in the x1.0 - 1.5 > range. Unfortunately, the linear scan allocator breaks > on most of my code. Is there a chance you can try cvs? I would be interested to get a simplified test case where the allocator breaks. A lot of

> On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > > > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > > } > > > > But the getRegClass method seems to expect a virtual register. Could > > someone fix this code for me? I could not find an example in the source of &...

...a > DAG that looks like > > load v4si <- extract_element 2 <- add -> load i32 > > I'd like to be able to generate > > load v4r0 > load r10 > add r11, r10, r2 <== subregister 2 of v4r0 I see that Evan has added getSubRegisters()/getSuperRegisters() to MRegisterInfo. This is what's needed in order to implement the register allocation constraint, but there's no way yet to pass the constraint through the operands from the DAG. There would need to be some way to specify that the SDOperand is referencing a subvalue of the produced value (perhaps a...

...I got around this problem of discovering the class of a physical register. I am using this code here: void PhiDeconstruction_Fer::add_move (MachineBasicBlock & mbb, unsigned src, unsigned dst) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const MRegisterInfo * reg_info = this->machine_function->getTarget().getRegisterInfo(); // TODO: verify if does not causes incorrect allocation: for(MRegisterInfo::regclass_iterator rcii = reg_info->regclass_begin(), rcie = reg_info->regclass_end(); rc...

..., coalesce virtual registers and remove identity moves > > ... > for (unsigned i = 0; i < mii->getNumOperands(); ++i) { > const MachineOperand& mop = mii->getOperand(i); > if (mop.isRegister() && mop.getReg() && > MRegisterInfo::isVirtualRegister(mop.getReg())) { > // replace register with representative register > unsigned reg = rep(mop.getReg()); > mii->SetMachineOperandReg(i, reg); > > LiveInterval &RegInt = getInterval(reg); > RegInt.weigh...