search for: mperttunen

On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 6474bd2a6d07..3d42cdbbe9c0 100644 --...

From: Thierry Reding <treding at nvidia.com> This set of patches adds support for fences to Tegra DRM and complements the fence FD support for Nouveau. Technically this isn't necessary for a fence-based synchronization loop with Nouveau because the KMS core takes care of all that, but engines behind host1x can use the IOCTL extensions provided here to emit fence FDs that in turn can be

...nkhorst at linux.intel.com> > Cc: "Ma?ra Canal" <mairacanal at riseup.net> > Cc: Mario Limonciello <mario.limonciello at amd.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Michal Simek <michal.simek at xilinx.com> > Cc: Mikko Perttunen <mperttunen at nvidia.com> > Cc: nouveau at lists.freedesktop.org > Cc: NXP Linux Team <linux-imx at nxp.com> > Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> > Cc: Pengutronix Kernel Team <kernel at pengutronix.de> > Cc: Philipp Zabel <p.zabel at pengutronix.de>...

...m> > > Cc: "Ma?ra Canal" <mairacanal at riseup.net> > > Cc: Mario Limonciello <mario.limonciello at amd.com> > > Cc: Maxime Ripard <mripard at kernel.org> > > Cc: Michal Simek <michal.simek at xilinx.com> > > Cc: Mikko Perttunen <mperttunen at nvidia.com> > > Cc: nouveau at lists.freedesktop.org > > Cc: NXP Linux Team <linux-imx at nxp.com> > > Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> > > Cc: Pengutronix Kernel Team <kernel at pengutronix.de> > > Cc: Philipp Zabel <p.zab...

On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 3d42cdbbe9c0..189ed80e21ff 100644 --- a/drivers/gpu/drm/nouve...

As with vga_init, this function doesn't make sense on non-PCI devices, and the Thunderbolt check in it dereferences a NULL pointer in that case. Add some code to skip this function when the device is not a PCI device. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_vga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index a4aacbc0cec8..b19dd4dc7099 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/dr...

...186, powergating is handled by the BPMP power domain provider > and the "legacy" powergating API is not available. Therefore skip > these calls if we are attached to a power domain. Thanks Mikko, Taken all 3 patches into my tree. Ben. > > Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> > --- > drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c > index 6474bd...

From: Mikko Perttunen <mperttunen at nvidia.com> Add an implementation of DMA fences backed by Host1x syncpoints, an interface to specify a prefence for job submissions. Before submission, prefences containing only Host1x syncpoints are waited by pushing wait commands to CDMA, whereas other fences are CPU-waited. Signed-off-b...

...Lankhorst <maarten.lankhorst at linux.intel.com> Cc: "Ma?ra Canal" <mairacanal at riseup.net> Cc: Mario Limonciello <mario.limonciello at amd.com> Cc: Maxime Ripard <mripard at kernel.org> Cc: Michal Simek <michal.simek at xilinx.com> Cc: Mikko Perttunen <mperttunen at nvidia.com> Cc: nouveau at lists.freedesktop.org Cc: NXP Linux Team <linux-imx at nxp.com> Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> Cc: Pengutronix Kernel Team <kernel at pengutronix.de> Cc: Philipp Zabel <p.zabel at pengutronix.de> Cc: Sascha Hauer <s.ha...

...ike.yoknis@hp.com> Mikel Astiz <mikel.astiz.oss@gmail.com> Mikel Astiz <mikel.astiz@bmw-carit.de> Mikhail Gruzdev <michail.gruzdev@gmail.com> Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Mikhail Pershin <mike.pershin@intel.com> Mikko Perttunen <mperttunen@nvidia.com> Mikko Tuumanen <mikko.tuumanen@qemsoftware.com> Mikko Vinni <mmvinni@yahoo.com> Miklos Szeredi <mszeredi@suse.cz> Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpatocka@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpato...

...ike.yoknis@hp.com> Mikel Astiz <mikel.astiz.oss@gmail.com> Mikel Astiz <mikel.astiz@bmw-carit.de> Mikhail Gruzdev <michail.gruzdev@gmail.com> Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Mikhail Pershin <mike.pershin@intel.com> Mikko Perttunen <mperttunen@nvidia.com> Mikko Tuumanen <mikko.tuumanen@qemsoftware.com> Mikko Vinni <mmvinni@yahoo.com> Miklos Szeredi <mszeredi@suse.cz> Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpatocka@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpato...

Does GK20A itself have any kind of thermal protection capabilities? Upstream SOCTHERM support is not yet available (though I have a driver in my tree), so we are thinking of disabling CPU DVFS on boards that don't have always-on active cooling for now. Same might be necessary for GPU as well. On 10/07/14 10:34, Alexandre Courbot wrote: > This series adds support for reclocking on

On 26.04.2018 15:41, Thierry Reding wrote: > On Wed, Apr 25, 2018 at 09:28:49AM -0600, Jordan Crouse wrote: >> On Wed, Apr 25, 2018 at 12:10:47PM +0200, Thierry Reding wrote: >>> From: Thierry Reding <treding at nvidia.com> >>> >>> Depending on the kernel configuration, early ARM architecture setup code >>> may have attached the GPU to a DMA/IOMMU