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On Tegra186, powergating is handled by the BPMP power domain provider and the "legacy" powergating API is not available. Therefore skip these calls if we are attached to a power domain. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 6474bd2a6d07..3d42cdb...

Hello everyone, it seems that GP10B support has regressed recently. With linux-next, I need to modify device/base.c to set .mmu = gp10b_mmu_new for GP10B (makes sense - I guess this was left as gf100_mmu_new as a typo) to probe. After that, running a trivial testcase (running a NOP method in 3D class) fails with [ 110.084649] nouveau 17000000.gpu: fifo: read fault at 0000011000 engine 06

On 06/09/2017 10:25 PM, Mikko Perttunen wrote: > On Tegra186, powergating is handled by the BPMP power domain provider > and the "legacy" powergating API is not available. Therefore skip > these calls if we are attached to a power domain. Thanks Mikko, Taken all 3 patches into my tree. Ben. > > Signed-off-by:...

On 07/10/2014 06:50 PM, Mikko Perttunen wrote: > Does GK20A itself have any kind of thermal protection capabilities? > Upstream SOCTHERM support is not yet available (though I have a driver > in my tree), so we are thinking of disabling CPU DVFS on boards that > don't have always-on active cooling for now. Same might be n...

...behind host1x can use the IOCTL extensions provided here to emit fence FDs that in turn can be used to synchronize their jobs with either the scanout engine or the GPU. See the following link for the Nouveau fence FD support series: https://patchwork.freedesktop.org/series/36361/ Thierry Mikko Perttunen (3): gpu: host1x: Add support for DMA fences drm/tegra: Add sync file support to submit interface drm/tegra: Support for sync file-based fences in submit drivers/gpu/drm/tegra/drm.c | 82 ++++++++++++--- drivers/gpu/host1x/Kconfig | 1 + drivers/gpu/host1x/Makefile...

...<maarten.lankhorst at linux.intel.com> > Cc: "Ma?ra Canal" <mairacanal at riseup.net> > Cc: Mario Limonciello <mario.limonciello at amd.com> > Cc: Maxime Ripard <mripard at kernel.org> > Cc: Michal Simek <michal.simek at xilinx.com> > Cc: Mikko Perttunen <mperttunen at nvidia.com> > Cc: nouveau at lists.freedesktop.org > Cc: NXP Linux Team <linux-imx at nxp.com> > Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> > Cc: Pengutronix Kernel Team <kernel at pengutronix.de> > Cc: Philipp Zabel <p.zabel at peng...

...linux.intel.com> > > Cc: "Ma?ra Canal" <mairacanal at riseup.net> > > Cc: Mario Limonciello <mario.limonciello at amd.com> > > Cc: Maxime Ripard <mripard at kernel.org> > > Cc: Michal Simek <michal.simek at xilinx.com> > > Cc: Mikko Perttunen <mperttunen at nvidia.com> > > Cc: nouveau at lists.freedesktop.org > > Cc: NXP Linux Team <linux-imx at nxp.com> > > Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> > > Cc: Pengutronix Kernel Team <kernel at pengutronix.de> > > Cc: Philipp...

On Tegra186 systems with certain firmware revisions, leaving the GPU in reset can cause a hang. To prevent this, don't leave the GPU in reset. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 3d42cdbbe9c0..189ed80e21ff 100644 --- a/driver...

As with vga_init, this function doesn't make sense on non-PCI devices, and the Thunderbolt check in it dereferences a NULL pointer in that case. Add some code to skip this function when the device is not a PCI device. Signed-off-by: Mikko Perttunen <mperttunen at nvidia.com> --- drivers/gpu/drm/nouveau/nouveau_vga.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index a4aacbc0cec8..b19dd4dc7099 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b...

...we need to select the GM200 path - the GP100 path seems to not to work - as mentioned in the first mail, we need to set .mmu = gp10b_mmu_new, - and in nouveau_mem_memory_target we need to return NVKM_MEM_TARGET_NCOH instead of NVKM_MEM_TARGET_HOST. Cheers, Mikko On 11/10/2017 11:27 PM, Mikko Perttunen wrote: > Hello everyone, > > it seems that GP10B support has regressed recently. With linux-next, I > need to modify device/base.c to set > >     .mmu = gp10b_mmu_new > > for GP10B (makes sense - I guess this was left as gf100_mmu_new as a > typo) to probe. After th...

...[0], NVKM_VMM_PAGE_SxHC }, +/* { 16, &gp100_vmm_desc_16[0], NVKM_VMM_PAGE_SxHC },*/ { 12, &gp100_vmm_desc_12[0], NVKM_VMM_PAGE_SxHx }, {} } on top of next-20171121 works at least for a simple test. Mikko On 11/11/2017 03:02 PM, Mikko Perttunen wrote: > Bisection status report: > > The latest commit I have gotten to work is > > 10842ba074e9 drm/nouveau: remove unused nouveau_fence_work() > > i.e. the first bad commit is > > d7722134b825 drm/nouveau: switch over to new memory and vmm interfaces > > Eve...

From: Mikko Perttunen <mperttunen at nvidia.com> Add an implementation of DMA fences backed by Host1x syncpoints, an interface to specify a prefence for job submissions. Before submission, prefences containing only Host1x syncpoints are waited by pushing wait commands to CDMA, whereas other fences are CPU-waited...

...t; Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com> Cc: "Ma?ra Canal" <mairacanal at riseup.net> Cc: Mario Limonciello <mario.limonciello at amd.com> Cc: Maxime Ripard <mripard at kernel.org> Cc: Michal Simek <michal.simek at xilinx.com> Cc: Mikko Perttunen <mperttunen at nvidia.com> Cc: nouveau at lists.freedesktop.org Cc: NXP Linux Team <linux-imx at nxp.com> Cc: "Pan, Xinhui" <Xinhui.Pan at amd.com> Cc: Pengutronix Kernel Team <kernel at pengutronix.de> Cc: Philipp Zabel <p.zabel at pengutronix.de> Cc: Sascha...

On 26.04.2018 15:41, Thierry Reding wrote: > On Wed, Apr 25, 2018 at 09:28:49AM -0600, Jordan Crouse wrote: >> On Wed, Apr 25, 2018 at 12:10:47PM +0200, Thierry Reding wrote: >>> From: Thierry Reding <treding at nvidia.com> >>> >>> Depending on the kernel configuration, early ARM architecture setup code >>> may have attached the GPU to a DMA/IOMMU

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

...e Yoknis <mike.yoknis@hp.com> Mikel Astiz <mikel.astiz.oss@gmail.com> Mikel Astiz <mikel.astiz@bmw-carit.de> Mikhail Gruzdev <michail.gruzdev@gmail.com> Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Mikhail Pershin <mike.pershin@intel.com> Mikko Perttunen <mperttunen@nvidia.com> Mikko Tuumanen <mikko.tuumanen@qemsoftware.com> Mikko Vinni <mmvinni@yahoo.com> Miklos Szeredi <mszeredi@suse.cz> Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpatocka@artax.karlin.mff.cuni.cz> Mikulas Pa...

...e Yoknis <mike.yoknis@hp.com> Mikel Astiz <mikel.astiz.oss@gmail.com> Mikel Astiz <mikel.astiz@bmw-carit.de> Mikhail Gruzdev <michail.gruzdev@gmail.com> Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Mikhail Pershin <mike.pershin@intel.com> Mikko Perttunen <mperttunen@nvidia.com> Mikko Tuumanen <mikko.tuumanen@qemsoftware.com> Mikko Vinni <mmvinni@yahoo.com> Miklos Szeredi <mszeredi@suse.cz> Mikulas Patocka <mikulas@artax.karlin.mff.cuni.cz> Mikulas Patocka <mpatocka@artax.karlin.mff.cuni.cz> Mikulas Pa...

Does GK20A itself have any kind of thermal protection capabilities? Upstream SOCTHERM support is not yet available (though I have a driver in my tree), so we are thinking of disabling CPU DVFS on boards that don't have always-on active cooling for now. Same might be necessary for GPU as well. On 10/07/14 10:34, Alexandre Courbot wrote: > This series adds support for reclocking on