Displaying 2 results from an estimated 2 matches for "movzwi".
Did you mean:
movzwl
2016 Jan 15
3
Help handling opaque AArch64 immediates
Hello LLVM,
I'm playing with a new ISD::OPAQUE instruction to make hoisting first
class and eliminate a lot of tweaky flag setting/checking around
opaque constants. It's going well for the IR and x86, but I now I
need to sort out details for all the other targets.
To start, can someone please advise on the AAarch64 equivalent of
these X86 patterns?
// Opaque values become mov immediate
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...strInfo.cpp:
```
// Return true if this instruction simply sets its single destination
register
// to zero. This is equivalent to a register rename of the zero-register.
bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
case AArch64::MOVZWi:
case AArch64::MOVZXi: // movz Rd, #0 (LSL #0)
if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
assert(MI.getDesc().getNumOperands() == 3 &&
MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
return true;...