Displaying 7 results from an estimated 7 matches for "movsuto_a_islo".
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...unction Printer ***:
# Machine code for function addproddivConst: Post SSA
Function Live Ins: %FA_ROFF1 in %vreg0
0B BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1
16B %vreg0<def> = COPY %FA_ROFF1; FPUaOffsetClass:%vreg0
32B %vreg2<def> = MOVSUTO_A_iSLo 1077936128; FPUaOffsetClass:%vreg2
48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2
64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
80B...
2018 May 04
0
How to constraint instructions reordering from patterns?
...t42: f32,ch,glue = CLPISD::COPY_TO_CALLER_A t41, TargetFrameIndex:i16<0>, t41:1
t43: ch = CLPISD::RET_FLAG t42:1
ISEL: Starting pattern match on root node: t50: i32 = Constant<1065353216>
Initial Opcode index to 415
TypeSwitch[i32] from 416 to 432
Morphed node: t50: i32 = MOVSUTO_A_iSLo TargetConstant:i32<1065353216>
def : Pat<(f32 fpimm:$imm),
(MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$imm))>;
def : Pat<(i32 imm:$imm),
(MOVSUTO_A_iSLo (trunc_imm i32:$imm))>;
===== Instruction selection ends:
Selected selection D...
2018 May 04
2
How to constraint instructions reordering from patterns?
...t; TargetFrameIndex:i16<0>, t41:1
>
> t43: ch = CLPISD::RET_FLAG t42:1
>
> ISEL: Starting pattern match on root node: t50: i32 = Constant<1065353216>
>
> Initial Opcode index to 415
>
> TypeSwitch[i32] from 416 to 432
>
> Morphed node: t50: i32 = MOVSUTO_A_iSLo TargetConstant:i32<1065353216>
>
> def: Pat<(f32 fpimm:$imm),
>
> (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$imm))>;
>
> def: Pat<(i32 imm:$imm),
>
> (MOVSUTO_A_iSLo (trunc_imm i32:$imm))>;
>
> ==...
2018 May 04
2
How to constraint instructions reordering from patterns?
Hi,
Is there a kind of scope mechanism in the instruction lowering pattern language in order to control where instructions are inserted or how they are later reordered during the SelectionDiag linearization?
I know the glue chain that stick instructions together. But such mechanism in not provided in instruction lowering pattern.
I'm facing many situations where some patterns are lowered into
2018 May 04
0
How to constraint instructions reordering from patterns?
...getFrameIndex:i16<0>, t41:1
>
> t43: ch = CLPISD::RET_FLAG t42:1
>
> ISEL: Starting pattern match on root node: t50: i32 =
> Constant<1065353216>
>
> Initial Opcode index to 415
>
> TypeSwitch[i32] from 416 to 432
>
> Morphed node: t50: i32 = MOVSUTO_A_iSLo TargetConstant:i32<1065353216>
>
> def: Pat<(f32 fpimm:$imm),
>
> (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32
> f32:$imm))>;
>
> def: Pat<(i32 imm:$imm),
>
> (MOVSUTO_A_iSLo (trunc_imm i32:$imm))>;
>
&...
2018 Apr 12
2
How to specify the RegisterClass of an IMPLICIT_DEF?
...'m implementing the built_vector as an IMPLICIT_DEF followed by INSERT_SUBREGs. This approach is the one of the SPARC architecture.
def : Pat<(build_vector (f32 fpimm:$a1), (f32 fpimm:$a2)),
(INSERT_SUBREG(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a1)), FPUaOffsetClass)), A_UNIT_PART),
(i32 (COPY_TO_REGCLASS (MOVSUTO_A_iSLo (bitcast_fpimm_to_i32 f32:$a2)), FPUaOffsetClass)), B_UNIT_PART)>;
This work quite well: an IMPLICIT_DEF:v2f32 is generated.
Selected selection DAG: BB#0 'vector2float...
2018 Sep 20
2
Errononous scheduling of COPY instruction.
...vestigate by myself... Could someone give me some clues?
After Instruction selection, here is part of the generated instruction.
NOP
MOV_AB_ro @s1, %fab_roff0
%6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
MOV_A_oo %6, def %5; FPUaOffsetClass:%6,%5
MOVSUTO_A_iSLo 24575, def %7; FPUaOffsetClass:%7
The order of instruction is very important: the COPY shall take place after the MOV_AB_ro!
But during Instruction scheduling, these two instructions have been permutated!
SU(18): NOP
SU(20): %6:fpuaoffsetclass = COPY %fab_roff0; FPUaOffsetClass:%6
SU(19):...