search for: movsd

...%xmm0, %xmm0 movl 112(%esp), %eax testl %eax, %eax je .LBB1_3 # BB#1: xorl %ebx, %ebx movl 108(%esp), %ecx movl 104(%esp), %edx xorl %esi, %esi .align 16, 0x90 .LBB1_2: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movsd (%edx,%ebx,8), %xmm2 addsd .LCPI1_0, %xmm2 movsd 16(%edx,%ebx,8), %xmm1 movsd %xmm1, (%esp) # 8-byte Spill movl %ebx, %edi addl $1, %edi addsd (%edx,%edi,8), %xmm2 movsd 136(%edx,%ebx,8), %xmm1 movsd %xmm1, 72(%esp) # 8-byte Spill movsd 128(%edx,%ebx,8), %xmm1 movsd %xmm...

...%xmm0, %xmm0 movl 112(%esp), %eax testl %eax, %eax je .LBB1_3 # BB#1: xorl %ebx, %ebx movl 108(%esp), %ecx movl 104(%esp), %edx xorl %esi, %esi .align 16, 0x90 .LBB1_2: # %.lr.ph.i # =>This Inner Loop Header: Depth=1 movsd (%edx,%ebx,8), %xmm2 addsd .LCPI1_0, %xmm2 movsd 16(%edx,%ebx,8), %xmm1 movsd %xmm1, (%esp) # 8-byte Spill movl %ebx, %edi addl $1, %edi addsd (%edx,%edi,8), %xmm2 movsd 136(%edx,%ebx,8), %xmm1 movsd %xmm1, 72(%esp) # 8-byte Spill movsd 128(%edx,%ebx,8), %xmm1 movsd %xmm...

....LBB6_55: # %merge128 movq 184(%rsp), %rcx movq %rax, 728(%rcx) movq 184(%rsp), %rax movq 728(%rax), %rcx movq %rcx, 736(%rax) movq 184(%rsp), %rax movq $0, 744(%rax) movq 184(%rsp), %rax movq $0, 752(%rax) movq 184(%rsp), %rax movq $0, 760(%rax) movq 176(%rsp), %rax movsd 5608(%rax), %xmm0 # xmm0 = mem[0],zero movq 184(%rsp), %rax mulsd 648(%rax), %xmm0 movsd 160(%rsp), %xmm1 # 8-byte Reload # xmm1 = mem[0],zero addsd %xmm0, %xmm1 movsd %xmm1, 672(%rax) movq 176(%rsp), %rax movsd 5648(%rax), %xmm0 # xmm0 = m...

...denom; if (num >= 0 && r.rem < 0) { r.quot++; r.rem -= denom; } return (r); } I get the following code emitted for the return if the alias line is present: LBB0_3: # %if.end movl 64(%esp), %eax movsd 24(%esp), %xmm0 movsd 32(%esp), %xmm1 movsd %xmm1, 8(%eax) movsd %xmm0, (%eax) addl $56, %esp popl %esi ret .Ltmp0: .size _lldiv, .Ltmp0-_lldiv .weak lldiv lldiv = _lldiv And this if it isn't: LBB0_3: # %if.end movl 64(%esp), %eax movsd 24(%esp), %xmm...

...C subpd xmm2,xmm6 002E04E0 movapd xmm1,xmm2 002E04E4 addpd xmm1,xmm0 002E04E8 mulpd xmm0,xmm0 002E04EC mulpd xmm2,xmm2 002E04F0 addpd xmm2,xmm0 002E04F4 sqrtpd xmm0,xmm2 002E04F8 addpd xmm0,xmm1 002E04FC addpd xmm2,xmm7 002E0500 movsd xmm4,mmword ptr ds:[2E0090h] 002E0508 movapd xmm1,xmm4 002E050C divsd xmm1,xmm2 002E0510 unpckhpd xmm2,xmm2 002E0514 movapd xmm3,xmm4 002E0518 divsd xmm3,xmm2 002E051C unpcklpd xmm1,xmm3 002E0520 mulpd xmm1,xmmword ptr ds:[2E00A0h] 002E0528 ad...

...es, and I came across a curious pattern. A smallish repro case is available at https://godbolt.org/z/Dsu1WI . In that case, the function Assembler::emit_arith receives a struct (Operand) by value and passes it by value to another function. That struct is 8 bytes long, so the -O3 generated code uses movsd to copy it up the stack. However, we end up with some loads that aren't needed, as in the following chunk: movsd xmm0, qword ptr [ecx] # xmm0 = mem[0],zero mov dword ptr [esp + 24], edx movsd qword ptr [esp + 40], xmm0 movsd xmm0, qword ptr [esp + 40] # xmm0 = mem[0],zero movsd qword ptr [esp...

I think there's a bug somewhere in TableGen for the X86 disassembler emitter. The following test: $ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble .section __TEXT,__text,regular,pure_instructions movsd (from llvm trunk) 0xF3 is the REP prefix, so the printed instruction should be 'rep movsd', however all that is printed is 'movsd'. It seems that there is an instruction enum for REP_MOVSD, but it isn't emitted in the generated .inc file? Is this a bug/oversight, or is there s...

...               r.quot++; >                r.rem -= denom; >        } >        return (r); > } > > I get the following code emitted for the return if the alias line is present: > > LBB0_3:                                # %if.end >        movl    64(%esp), %eax >        movsd   24(%esp), %xmm0 >        movsd   32(%esp), %xmm1 >        movsd   %xmm1, 8(%eax) >        movsd   %xmm0, (%eax) >        addl    $56, %esp >        popl    %esi >        ret > .Ltmp0: >        .size   _lldiv, .Ltmp0-_lldiv > > >        .weak   lldiv > lldiv = _...

From: Mihai Don?u <mdontu at bitdefender.com> This is needed in order to be able to support guest code that uses movsd to write into pages that are marked for write tracking. Signed-off-by: Mihai Don?u <mdontu at bitdefender.com> Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com> --- arch/x86/kvm/emulate.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-)...

...Andrew Ruef <awruef at umd.edu> wrote: > I think there's a bug somewhere in TableGen for the X86 disassembler > emitter. The following test: > > $ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble > .section __TEXT,__text,regular,pure_instructions > movsd > > (from llvm trunk) > > 0xF3 is the REP prefix, so the printed instruction should be 'rep > movsd', however all that is printed is 'movsd'. It seems that there is > an instruction enum for REP_MOVSD, but it isn't emitted in the > generated .inc file? Is th...

Hmm, I'm not able to get those .ll files to compile if I disable SSE and I end up with SSE instructions(including sqrtpd) if I don't disable it. On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote: > Is there something specifically required to enable SSE? If it's not > detected as available (based from the target triple?) then I don't think

...is passed to the function call. 402a91: 48 8d bc 1c 48 02 00 lea 0x248(%rsp,%rbx,1),%rdi 402a98: 00 402a99: e8 82 e0 ff ff callq 400b20 <llvm_memory_profiling at plt> /home/xl10/llvm/test//luleshOMP-0611.cc:1974 402a9e: f2 0f 10 84 1c 48 02 movsd 0x248(%rsp,%rbx,1),%xmm0 402aa5: 00 00 402aa7: f2 0f 11 84 24 b8 01 movsd %xmm0,0x1b8(%rsp) However, due to instruction scheduling, the following instruction of the function call is not always the desired memory access instruction. For example, in the following code, the memo...

...rc -fobjc-runtime-has-weak -fobjc-fragile-abi -fdiagnostics show-option -fcolor-diagnostics -o test.s -x c test.c .def _f; .scl 2; .type 32; .endef .text .globl _f .align 16, 0x90 _f: # @f # BB#0: movl $-800, %eax # imm = 0xFFFFFFFFFFFFFCE0 movsd _DA, %xmm0 .align 16, 0x90 LBB0_1: # =>This Inner Loop Header: Depth=1 movsd _X+800(%eax), %xmm1 mulsd %xmm0, %xmm1 movsd _Y+800(%eax), %xmm2 subsd %xmm1, %xmm2 movsd %xmm2, _Y+800(%eax) addl $8, %eax jne LBB0_1 # BB#2: xorl %eax, %eax ret .data .globl...

...1312 users should not rely upon it. Assigning to YYVAL 1313 unconditionally makes the parser a bit smaller, and it avoids a 1314 GCC warning that YYVAL may be used uninitialized. */ 1315 yyval = yyvsp[1-yylen]; => 0x0000000000400c2d <rpcalc_parse+653>: movsd xmm0,QWORD PTR [rbx+rax*8] 0x0000000000400c32 <rpcalc_parse+658>: movsd QWORD PTR [rbp-0x808],xmm0 As far as I understand it, assigning to eax zero-extends to rax. However, eax holds the result of "1-yylen" which is expected to be negative, so it should be sign-extended...

I want to write a pattern that looks something like this: def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst), (MOVSDmr ADD64ri8(addr:$dst, imm:8), ( SHUFPDrri (VR128:$src, (MOVSDmr addr:$dst, FR64:$src))), imm:3) So I want to convert an unaligned vector store to a scalar store, a shuffle and a scalar store. There are several question I have: - Is the imm:3 syntax correct? Basically I want to hard-...

...handle it. void fool( int long n ) { double w[268435600]; double z[268435600]; unsigned long i; for ( i = 0; i < n; i++ ) { w[i] = 1.0; z[i] = 2.0; } printf(" n: %lld, W %g Z %g\n", n, w[1], z[1] ); } Here's one of the offending instructions produced by 2.9: movsd -2147482472(%rsp), %xmm0 Fixing the displacement overflow is pretty easy. It's just a matter of changing a few variable types in LLVM from unsigned to uint64_t in the functions that calculate the stack offsets. The real trouble I'm having is finding a good place to break up the displacem...

...or the user, and simplifies reading an llvm-mca analysis report later. When this code is compiled, the region markers (the mca_code_region markers) are transformed into assembly labels. While the markers are presented as function calls, in reality they are no-ops. test: pushq %rbp movq %rsp, %rbp movsd %xmm0, -8(%rbp) movsd %xmm1, -16(%rbp) .Lmca_code_region_start_0: # LLVM-MCA-START ID: 42 xorps %xmm0, %xmm0 movsd %xmm0, -24(%rbp) movsd -8(%rbp), %xmm0 mulsd -16(%rbp), %xmm0 addsd -24(%rbp), %xmm0 movsd %xmm0, -24(%rbp) .Lmca_code_region_end_0: # LLVM-MCA-END ID: 42 movsd -24(%rbp), %xmm0 popq %...

...sed to the function call. 402a91: 48 8d bc 1c 48 02 00 lea 0x248(%rsp,%rbx,1),%rdi 402a98: 00 402a99: e8 82 e0 ff ff callq 400b20 <llvm_memory_profiling at plt> /home/xl10/llvm/test//luleshOMP-0611.cc:1974 402a9e: f2 0f 10 84 1c 48 02 movsd 0x248(%rsp,%rbx,1),%xmm0 402aa5: 00 00 402aa7: f2 0f 11 84 24 b8 01 movsd %xmm0,0x1b8(%rsp) However, due to instruction scheduling, the following instruction of the function call is not always the desired memory access instruction. For example, in the following code, th...

...5b50 MOV32mi %EBP, 1, %NOREG, -224, <ga:DataStore> %EAX = MOV32rm %EBP, 1, %NOREG, -224 %EAX = ADD32ri8 %EAX, 40 MOV32mi %EAX, 1, %NOREG, 0, 0 MOV32mi %EAX, 1, %NOREG, 4, 1075576832 %ESP = SUB32ri %ESP, 16 %XMM0 = CVTSI2SDrr %EDI MOVSDmr %ESP, 1, %NOREG, 0, %XMM0 MOV32mr %EBP, 1, %NOREG, -268, %ESP ADD32mi8 %EBP, 1, %NOREG, -268, 4294967288 %ESP = MOV32rm %EBP, 1, %NOREG, -268 %ESI = MOV32rm %EBP, 1, %NOREG, -224 %ESI = ADD32ri8 %ESI, 16 MOV32mi %ESI, 1, %NOREG, 0, 0 MOV32mi...

...# ??? what insn in X86InstrInfo.td? .Llabel1: movq %rsp, %rbp # ??? what insn in X86InstrInfo.td? .Llabel2: movq %rdi, -16(%rbp) # ??? what insn in X86InstrInfo.td? movq -16(%rbp), %rax # ??? what insn in X86InstrInfo.td? cvtsi2sdq %rax, %xmm0 # ??? what insn in X86InstrInfo.td? movsd %xmm0, -8(%rbp) # ??? what insn in X86InstrInfo.td? movsd -8(%rbp), %xmm0 # ??? what insn in X86InstrInfo.td? popq %rbp # ??? what insn in X86InstrInfo.td? ret --- With best regards, Konstantin