search for: movh

On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: > For example, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (b...

...rhaps we should > discuss what it is supposed to look like? Don't throw the Greenspunning term around unless you really mean it. The problem I solved via multidefs was this: how does one write a set of Pat<> patterns in a generic way? For example, I want to be able to do this: defm MOVH : vs1x_fps_binary_vv_node_rmonly< 0x16, "movh", undef, 0, // rr [(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert...

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

Jakob Stoklund Olesen <jolesen at apple.com> writes: > On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: > >> For example, I want to be able to do this: >> >> defm MOVH : >> vs1x_fps_binary_vv_node_rmonly< >> 0x16, "movh", undef, 0, >> // rr >> [(undef)], >> // rm >> [(set DSTREGCLASS:$dst, >> (DSTTYPE (movlhps SRCREGCLASS:$src1, >>...

...ovzbl 1(%rdi), %ecx movb %al, z(%rip) movb %cl, z+1(%rip) incb %al shll $8, %ecx movzbl %al, %eax orl %ecx, %eax retq I was hoping it would do something along the lines of movb (%rdi), %al movb 1(%rdi), %ah movh %ax, z(%rip) incb %al retq Why is the x86 backend not getting this code? Does it know that AH:AL = AX? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

On Oct 6, 2011, at 12:42 PM, David A. Greene wrote: > Jakob Stoklund Olesen <jolesen at apple.com> writes: > >> On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: >> >>> For example, I want to be able to do this: >>> >>> defm MOVH : >>> vs1x_fps_binary_vv_node_rmonly< >>> 0x16, "movh", undef, 0, >>> // rr >>> [(undef)], >>> // rm >>> [(set DSTREGCLASS:$dst, >>> (DSTTYPE (movlhps SRCREGCLASS:$src1,...

...gt; movb %cl, z+1(%rip) > incb %al > shll $8, %ecx > movzbl %al, %eax > orl %ecx, %eax > retq > > >I was hoping it would do something along the lines of > > movb (%rdi), %al > movb 1(%rdi), %ah > movh %ax, z(%rip) > incb %al > retq > > >Why is the x86 backend not getting this code? Does it know that AH:AL = >AX? > >-Krzysztof > > > >-- >Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >hosted by The Linux Foundation >___________...

...ip) > movb %cl, z+1(%rip) > incb %al > shll $8, %ecx > movzbl %al, %eax > orl %ecx, %eax > retq > > > I was hoping it would do something along the lines of > > movb (%rdi), %al > movb 1(%rdi), %ah > movh %ax, z(%rip) > incb %al > retq > > > Why is the x86 backend not getting this code? Try enabling the sub-register liveness feature. I am guessing we think we cannot use the same register for the low and high part. Though, I would need to see the machine instrs to be sure. >...

...t; incb %al >> shll $8, %ecx >> movzbl %al, %eax >> orl %ecx, %eax >> retq >> >> >> I was hoping it would do something along the lines of >> >> movb (%rdi), %al >> movb 1(%rdi), %ah >> movh %ax, z(%rip) >> incb %al >> retq >> >> >> Why is the x86 backend not getting this code? > > Try enabling the sub-register liveness feature. I am guessing we think we cannot use the same register for the low and high part. > Though, I would need to see the ma...

Hi Renato, > > I'm trying to add pseudo 64-bit load and store instructions for AArch64, which > > should have latencies set to "1" while being otherwise exactly the same as > > normal load and store instructions. > > Can I ask why would you need that? This is the only way I found to stop Machine Instruction Scheduler from reordering load and store

greened at obbligato.org (David A. Greene) writes: > The problem I solved via multidefs was this: how does one write a set of > Pat<> patterns in a generic way? > > For example, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DS...

...%al > > shll $8, %ecx > > movzbl %al, %eax > > orl %ecx, %eax > > retq > > > > > >I was hoping it would do something along the lines of > > > > movb (%rdi), %al > > movb 1(%rdi), %ah > > movh %ax, z(%rip) > > incb %al > > retq > > > > > >Why is the x86 backend not getting this code? Does it know that AH:AL = > >AX? > > > >-Krzysztof > > > > > > > >-- > >Qualcomm Innovation Center, Inc. is a member of Code...

...> > movzbl %al, %eax > > orl %ecx, %eax > > retq > > > > > >I was hoping it would do something along the lines of > > > > movb (%rdi), %al > > movb 1(%rdi), %ah > > movh %ax, z(%rip) > > incb %al > > retq > > > > > >Why is the x86 backend not getting this code? Does it know that > AH:AL = > >AX? > > > >-Krzysztof > > > > > > > >-- >...

...l %al, %eax >> > orl %ecx, %eax >> > retq >> > >> > >> >I was hoping it would do something along the lines of >> > >> > movb (%rdi), %al >> > movb 1(%rdi), %ah >> > movh %ax, z(%rip) >> > incb %al >> > retq >> > >> > >> >Why is the x86 backend not getting this code? Does it know that >> AH:AL = >> >AX? >> > >> >-Krzysztof >> > >> > &...

...rhaps we should > discuss what it is supposed to look like? Don't throw the Greenspunning term around unless you really mean it. The problem I solved via multidefs was this: how does one write a set of Pat<> patterns in a generic way? For example, I want to be able to do this: defm MOVH : vs1x_fps_binary_vv_node_rmonly< 0x16, "movh", undef, 0, // rr [(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert...

...2011, at 12:42 PM, David A. Greene wrote: > >> Jakob Stoklund Olesen <jolesen at apple.com> writes: >> >>> On Oct 6, 2011, at 7:59 AM, David A. Greene wrote: >>> >>>> For example, I want to be able to do this: >>>> >>>> defm MOVH : >>>> vs1x_fps_binary_vv_node_rmonly< >>>>   0x16, "movh", undef, 0, >>>>          // rr >>>>          [(undef)], >>>>          // rm >>>>          [(set DSTREGCLASS:$dst, >>>>                (DSTTYPE...

...orl %ecx, %eax >>> > retq >>> > >>> > >>> >I was hoping it would do something along the lines of >>> > >>> > movb (%rdi), %al >>> > movb 1(%rdi), %ah >>> > movh %ax, z(%rip) >>> > incb %al >>> > retq >>> > >>> > >>> >Why is the x86 backend not getting this code? Does it know that >>> AH:AL = >>> >AX? >>> > >>> >-Krzysztof...

...shll $8, %ecx >>> movzbl %al, %eax >>> orl %ecx, %eax >>> retq >>> >>> >>> I was hoping it would do something along the lines of >>> >>> movb (%rdi), %al >>> movb 1(%rdi), %ah >>> movh %ax, z(%rip) >>> incb %al >>> retq >>> >>> >>> Why is the x86 backend not getting this code? >> >> Try enabling the sub-register liveness feature. I am guessing we think we cannot use the same register for the low and high part. >> T...

...;>> > retq >>>> > >>>> > >>>> >I was hoping it would do something along the lines of >>>> > >>>> > movb (%rdi), %al >>>> > movb 1(%rdi), %ah >>>> > movh %ax, z(%rip) >>>> > incb %al >>>> > retq >>>> > >>>> > >>>> >Why is the x86 backend not getting this code? Does it know that >>>> AH:AL = >>>> >AX? >>>> &gt...