Displaying 20 results from an estimated 54 matches for "mov32rm".
2007 Dec 19
0
[LLVMdev] JIT Stub Problem
...of temp2.loc, the error does not occur.
In addition, here's what the MachineFunction code and the generated machine code look like for these basic blocks.
falseBlock (0xa60cb18, LLVM BB @0xa5ce378, ID#81):
Predecessors according to CFG: 0xa60ca80
%EAX = MOV32ri 617
%EBX = MOV32rm %EBP, 1, %NOREG, -12
%EDI = MOV32rm %EBP, 1, %NOREG, -8
%ESI = MOV32rm %EBP, 1, %NOREG, -4
%ESP = MOV32rr %EBP
%EBP = POP32r
RET
codeRepl (0xa5f4148, LLVM BB @0xa5ce310, ID#82):
Predecessors according to CFG: 0xa60ca80
%EDI = INC32r %EDI...
2010 Oct 29
1
[LLVMdev] [LLVMDev] Register Allocation and Kill Flags
...e below is just an example from test\CodeGen\X86\xor.ll
# Machine code for function test3:
Frame Objects:
fi#-2: size=4, align=4, fixed, at location [SP+8]
fi#-1: size=4, align=8, fixed, at location [SP+4]
Function Live Outs: %EAX
BB#0: derived from LLVM BB %entry
%reg16385<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0;
mem:LD4[FixedStack-2] GR32:%reg16385
%reg16384<def> = MOV32rm <fi#-1>, 1, %reg0, 0, %reg0;
mem:LD4[FixedStack-1] GR32:%reg16384
%reg16388<def> = MOV32ri 1; GR32:%reg16388
%reg16392<def> = XOR32ri %reg16385, 4294967294,...
2006 Jun 26
2
[LLVMdev] Mapping bytecode to X86
...0][1];
sum = (i + j) * j;
printf("Sum = %d\n", sum);
}
that maps to this llvm bytecode:
entry (0xa785590, LLVM BB @0xa77ebf8):
FNSTCW16m <fi#0>, 1, %NOREG, 0
MOV8mi <fi#0>, 1, %NOREG, 1, 2
FLDCW16m <fi#0>, 1, %NOREG, 0
%reg1024 = MOV32rm <fi#-2>, 1, %NOREG, 0
%reg1025 = MOV32rm %reg1024, 1, %NOREG, 0
%reg1026 = MOVSX32rm8 %reg1025, 1, %NOREG, 0
%reg1027 = MOVSX32rm8 %reg1025, 1, %NOREG, 1
ADJCALLSTACKDOWN 8
%reg1028 = ADD32rr %reg1026, %reg1027
%reg1029 = IMUL32rr %reg1028, %reg...
2007 Dec 20
1
[LLVMdev] Code Generation Problem llvm 1.9
...l %7, label %entry.bb19_crit_edge.i270, label %bb.preheader.i271
It gets converted to the following MachineBasicBlock
__exp.exit (0x8c58628, LLVM BB @0x8c1c558, ID#21):
Predecessors according to CFG: 0x8c53a90 0x8c55b50
MOV32mi %EBP, 1, %NOREG, -224, <ga:DataStore>
%EAX = MOV32rm %EBP, 1, %NOREG, -224
%EAX = ADD32ri8 %EAX, 40
MOV32mi %EAX, 1, %NOREG, 0, 0
MOV32mi %EAX, 1, %NOREG, 4, 1075576832
%ESP = SUB32ri %ESP, 16
%XMM0 = CVTSI2SDrr %EDI
MOVSDmr %ESP, 1, %NOREG, 0, %XMM0
MOV32mr %EBP, 1, %NOREG, -268, %ESP
A...
2009 Nov 24
0
[LLVMdev] X86InstrInfo::GetInstSizeInBytes() calculating incorrect size
...her computer I can
test this on to see if that's it though. If this turns out to be a bug,
rather than some misuse/misinterpretation of the function on my part I can
resubmit it via that channel.
The instructions I've noticed this occurring for are:
MOV32mi, LEA32r, MOV32mr, and MOV32rm
The length of LEA32r is calculated correctly some of the time. Same for
MOV32mr and MOV32rm. The length of MOV32mi seems to always be wrong.
An example breakdown of emitted Machine Instructions - the machine
instructions are those outputted when I pass the -debug option to lli.exe
(form...
2008 Mar 19
2
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
...}, // Inst #5 = INSERT_SUBREG
THe sixth field is zero, which means it doesn't have the the
MayLoad flag set.
x86-64 does have a few variants of INSERT_SUBREG, and one of
them does have a load:
def : Pat<(i64 (anyext (loadi32 addr:$src))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
x86_subreg_32bit)>;
This isn't currently being reflected in the InstrInfo tables.
Naively, it seems like we should add a separate INSERT_SUBREGrm
instruction, and so on, or something like that, in order to be able
to have accu...
2017 Aug 02
2
Efficiently ignoring upper 32 pointer bits whendereferencing
...s an
> iPTR type in X86InstrInfo.td which I assume is expanded to 4 or 8
> bytes depending on if 32/64 bit mode is active:
> def addr : ComplexPattern<iPTR, 5, "selectAddr", [],
> [SDNPWantParent]>;
> The derefencing mov instruction looks like this:
> def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
> "mov{l}\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
> So it expects a source address of type 'addr' which is 8 bytes. This
> leads to the...
2009 Dec 16
1
[LLVMdev] incorrect x86 instruction size calculation
...y re-implementing SFI for the LLVM x86 backend
based on the Google NaCl project.
However, in trying to implement 32-byte code alignment,
X86InstrInfo::GetInstSizeInBytes() is returning incorrect instruction sizes
for certain instructions (that I have seen so far): MOV32mi, LEA32r,
MOV32mr, and MOV32rm.
MOV32mi is always calculated incorrectly while the remaining 3 are sometimes
calculated incorrectly. Just to illustrate:
8d 9c 24 30 0a 00 00 LEA32r
calculated length: 7 ok
8d 6c 24 28 LEA32r
calculated length:...
2017 Aug 02
2
Efficiently ignoring upper 32 pointer bits when dereferencing
...cally, addresses are defined as an
iPTR type in X86InstrInfo.td which I assume is expanded to 4 or 8 bytes
depending on if 32/64 bit mode is active:
def addr : ComplexPattern<iPTR, 5, "selectAddr", [],
[SDNPWantParent]>;
The derefencing mov instruction looks like this:
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"mov{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
So it expects a source address of type 'addr' which is 8 bytes. This
leads to the following code bein...
2015 Mar 18
6
[LLVMdev] string input for the integrated assembler
...variable length instructions and a laborious hierarchy of
tblgen AsmOperands to do the job. Assembly and disassembly with
llvm-mc and llvm-objdump work fine.
As a simplification, the compiler deals almost exclusively in pseudo
instructions. By x86 analogy, using pseudos to unfold a TEST32rm into
MOV32rm + TEST32rr means I can skip the complex operand fitting effort
needed to pick specific machine instructions. There are many such
examples where handling real instructions would become a gross
overload.
One drawback of this approach is that the integrated assembler
receives only unexpanded pseudos...
2011 Aug 06
0
[LLVMdev] How to differ from read and write operations for general stack objects
The following is the code fragment after "# *** IR Dump Before
Prolog/Epilog Insertion & Frame Finalization ***:".
* MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 0 *
* MOV32mr <fi#2>, 1, %reg0, 0, %reg0, %ECX<kill>*
* %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0*
* MOV32mr %reg0, 1, %reg0, <ga:@one+4>, %reg0, %EAX<kill>*
* %EAX<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0*
* ADJCALLSTACKDOWN32 8, %ESP<imp-def,dead>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>*
* %ECX<def> = MOV32rr %ESP...
2008 Mar 19
0
[LLVMdev] SUBREG instructions and mayLoad/mayStore/etc.
...gs set. If it's not coalesced away, it's eventually
lowered into a move.
>
>
> x86-64 does have a few variants of INSERT_SUBREG, and one of
> them does have a load:
>
> def : Pat<(i64 (anyext (loadi32 addr:$src))),
> (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
>
> x86_subreg_32bit)>;
>
>
> This isn't currently being reflected in the InstrInfo tables.
> Naively, it seems like we should add a separate INSERT_SUBREGrm
> instruction, and so on, or something like tha...
2010 May 18
2
[LLVMdev] Fast register allocation
...ds spills and restores into other instructions. RAFast doesn't bother because debug builds have very few spills.
RAFast uses more aggressive hinting by peeking at future instructions. This helps reduce the number of register copies when setting up parameters for a call:
%reg1028<def> = MOV32rm <fi#2>, 1, %reg0, 0, %reg0
%reg1029<def> = MOV32rm <fi#2>, 1, %reg0, 4, %reg0
ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def>, %RSP<imp-use>
%reg1030<def> = LEA64r %RIP, 1, %reg0, <ga:@.str>
%reg1031<def> = MOV8r0 %EFLAGS<imp-def,de...
2013 Feb 08
2
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...lt;imp-use> ; line 1
%vreg187<def> = COPY %ESP; GR32:%vreg187
; line 2
MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack]
GR32:%vreg187 FR64:%vreg36 ; line 3
%vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108]
GR32:%vreg188,%vreg112
%vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111]
GR32:%vreg189,%vreg112
%vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg; mem:LD8[%85]
FR64:%vreg190
%vreg191<def> = MOVSDrm...
2009 Apr 22
2
[LLVMdev] Def/Kill flags for subregisters
...his seems to be the assumption of the register scavenger.
3. A register must be killed before it can be defined again.
Is this theory correct?
If so, it would be necessary to sprinkle extra <imp-use,kill> here and
there, like I have done above.
Here is an X86 example:
%EAX<def> = MOV32rm %ESP, 1, %noreg, 8, %noreg, Mem:LD(4,4)
[FixedStack-2 + 0]
%ECX<def> = MOV32rm %ESP, 1, %noreg, 4, %noreg, Mem:LD(4,16)
[FixedStack-1 + 0]
%EDX<def> = LEA32r %ECX, 1, %EAX, 0
%EDX<def> = ADD32rr %EDX, %EAX<kill>, %EFLAGS<imp-def,dead>
%EAX<def> = MOVZX32r...
2013 Mar 18
5
[LLVMdev] Hit a snag while attempting to write a backend - any advice?
...%vreg1<def> = COPY %R1<kill>; GR32:%vreg1
%vreg0<def> = COPY %R0; GR32:%vreg0
MOV32mr <fi#1>, 0, %vreg0<kill>; mem:ST4[%c.addr] GR32:%vreg0
MOV32mr <fi#2>, 0, %vreg1<kill>; mem:ST4[%d.addr] GR32:%vreg1
%vreg2<def> = MOV32rm <fi#1>, 0; mem:LD4[%c.addr] GR32:%vreg2
%vreg3<def> = CMPfri %vreg2<kill>, 0; SR1:%vreg3 GR32:%vreg2
JCC %vreg3<kill>, <BB#2>; SR1:%vreg3
JMP <BB#1>, %R0<imp-use>
Successors according to CFG: BB#1(20) BB#2(12)
BB#1: derived from...
2013 Feb 08
0
[LLVMdev] help with X86 DAG->DAG Instruction Selection
...%vreg187<def> = COPY %ESP; GR32:%vreg187 ; line 2
> MOVSDmr %vreg187, 1, %noreg, 0, %noreg, %vreg36; mem:ST8[Stack] GR32:%vreg187 FR64:%vreg36 ; line 3
> %vreg188<def> = MOV32rm %vreg112, 1, %noreg, 252, %noreg; mem:LD4[%108] GR32:%vreg188,%vreg112
> %vreg189<def> = MOV32rm %vreg112, 1, %noreg, 256, %noreg; mem:LD4[%111] GR32:%vreg189,%vreg112
> %vreg190<def> = MOVSDrm <fi#0>, 1, %noreg, 120, %noreg; mem:LD8[%85] FR64:%vreg190
> %vreg191<de...
2011 Jan 29
1
[LLVMdev] The type or size of virtual registers in machineinstr
...perand is a register). For
example, what is the size of reg16385 in the following MachineInstr. I know
now in the llvm bitcode, the type of a Instruction could be obtained from
the Value::GetType(), but what is the counterpart in MachineInstr (not
derived from class Value)?
%reg16385<def> = MOV32rm <fi#0>, 1, %reg0, 0, %reg0; mem:LD4[%x_addr]
GR32:%reg16385
--
Best regards,
Li Qingan
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2011 Jan 16
1
[LLVMdev] About register allocation
...tion:
MOV32mi <fi#2>, 1, %reg0, 0, %reg0, 3; mem:ST4[%a]
MOV32mi <fi#3>, 1, %reg0, 0, %reg0, 5; mem:ST4[%b]
MOV32mi <fi#5>, 1, %reg0, 0, %reg0, 4; mem:ST4[%d]
MOV32mi <fi#6>, 1, %reg0, 0, %reg0, 100; mem:ST4[%x]
%reg16384<def> = MOV32rm <fi#3>, 1, %reg0, 0, %reg0; mem:LD4[%b]
GR32:%reg16384
CMP32mr <fi#2>, 1, %reg0, 0, %reg0, %reg16384<kill>,
%EFLAGS<imp-def>; mem:LD4[%a] GR32:%reg16384
JLE_4 <BB#2>, %EFLAGS<imp-use,kill>
The machine code after register allocation:
MOV...
2010 Sep 01
1
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 11:14 AM, Dale Johannesen wrote:
>
> On Sep 1, 2010, at 6:25 AMPDT, Argyrios Kyrtzidis wrote:
>
>> The attached .ll files seem equivalent, but the resulting asm from
>> 'opt-fail.ll' causes a crash to webkit.
>> I suspect the usage of registers is wrong, can someone take a look ?
>
> Yes, the code here is wrong:
>
>> movl