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2016 Sep 20
7
RFC: Implement variable-sized register classes
...guish two objects of class HwMode if they have different names, regardless of what sets of predicates they contain. One way to think of it is that the name of the object would serve as a tag denoting the hardware mode. In the example of the AddReg instruction, we could define two modes: def Mode64: Mode<[...]>; def Mode128: Mode<[...]>; but so far there would not be much more that we could do. 2. To make a use of the mode information, provide a class to associate a HwMode object with a particular value. This will be done by having two lists: one with HwMode objects and ano...
2016 Sep 24
2
RFC: Implement variable-sized register classes
On 9/24/2016 7:20 AM, Alex Bradbury wrote: > My concern is that all of the above adds yet more complexity to what > is already (in my view) a fairly difficult part of LLVM to understand. > The definition of MyRegisterClass is not so bad though, and perhaps it > doesn't matter how it works under the hood to the average backend > writer. I agree with the complexity, but I would