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...e get: Indeed such padding is a known (programmer) optimization to effectively have power-of-2 strides and/or alignment. > So, unfortunately, it turns out I don't have access to DENBench. If you like we could test your patch to see how it (mis)behaves. From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Thursday, August 18, 2016 03:57 To: Zaks, Ayal <ayal.zaks at intel.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Renato Golin <renato.golin at linaro.org>; Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh <Ashutosh.Nema at...

...= y; > > *out++ = (unsigned char)i; > > *out++ = (unsigned char)q; > > } > > } > > > > but you’d currently need to force it to vectorize to overcome its expected > cost. > > > > Ayal. > > > > *From:* Michael Kuperstein [mailto:mkuper at google.com] > *Sent:* Wednesday, August 17, 2016 00:51 > *To:* Zaks, Ayal <ayal.zaks at intel.com>; Demikhovsky, Elena < > elena.demikhovsky at intel.com> > *Cc:* Renato Golin <renato.golin at linaro.org>; Matthew Simpson < > mssimpso at codeaurora.org>; Ne...

...o turn this on, and then, if regressions show up on anyone's radar (where we can actually get a reproducer), turn it off again and go back to analysis. But I'd strongly prefer to "prefetch" the problem. Thanks, Michael On Wed, Aug 10, 2016 at 4:32 PM, Michael Kuperstein <mkuper at google.com> wrote: > So, unfortunately, it turns out I don't have access to DENBench. > > Do you happen to have a reduced example that gets pessimized by this? > > On Tue, Aug 9, 2016 at 11:25 AM, Michael Kuperstein <mkuper at google.com> > wrote: > >> Th...

...n 32-bit mode. > > > > One place to find them, using the default BaseT::getInterleavedMemoryOpCost(), > is DENBench’s RGB conversions. > > > > Ayal. > > > > *From:* Demikhovsky, Elena > *Sent:* Monday, August 08, 2016 00:09 > *To:* Michael Kuperstein <mkuper at google.com>; Renato Golin < > renato.golin at linaro.org> > *Cc:* Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh < > Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rotateright.com>; llvm-dev < > llvm-dev at lists.llvm.org>; Zaks, Aya...

We checked the gathered data again. All regressions that we see are in 32-bit mode. The 64-bit mode looks good overall. - Elena From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Saturday, August 06, 2016 02:56 To: Renato Golin <renato.golin at linaro.org> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Matthew Simpson <mssimpso at codeaurora.org>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; Sanjay Patel <spatel at rot...

On 6 August 2016 at 00:18, Michael Kuperstein <mkuper at google.com> wrote: > I agree that we can get *more* improvement with better cost modeling, but > I'd expect to be able to get *some* improvement the way things are right > now. Elena said she saw "some" improvements. :) > That's why I'm curious about where...

...s. Regards, Ashutosh From: Nema, Ashutosh Sent: Wednesday, March 1, 2017 10:42 AM To: 'Daniel Berlin' <dberlin at dberlin.org> Cc: anemet at apple.com; Hal Finkel <hfinkel at anl.gov>; Zaks, Ayal <ayal.zaks at intel.com>; Renato Golin <renato.golin at linaro.org>; mkuper at google.com; Mehdi Amini <mehdi.amini at apple.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: RE: [llvm-dev] [Proposal][RFC] Epilog loop vectorization Sorry I misunderstood, gvn/newgvn/gvnhoist cannot help here as these checks are not dominated by all paths. Regards, Ashutosh...

Thanks Michael and Dibyendu for doing the experimentation and bringing this up to our attention. It might be the case what Matt described here. I will take a look at it. Farhana From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Wednesday, December 14, 2016 9:56 AM To: Das, Dibyendu <Dibyendu.Das at amd.com>; Aleen, Farhana A <farhana.a.aleen at intel.com> Cc: Matthew Simpson <mssimpso at codeaurora.org>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Enabling scalarized condition...

...apple.com>; Hal Finkel >> <hfinkel at anl.gov <mailto:hfinkel at anl.gov>>; Zaks, Ayal >> <ayal.zaks at intel.com <mailto:ayal.zaks at intel.com>>; Renato Golin >> <renato.golin at linaro.org >> <mailto:renato.golin at linaro.org>>;mkuper at google.com >> <mailto:mkuper at google.com>; Mehdi Amini <mehdi.amini at apple.com >> <mailto:mehdi.amini at apple.com>>; llvm-dev <llvm-dev at lists.llvm.org >> <mailto:llvm-dev at lists.llvm.org>> >> *Subject:*RE: [llvm-dev] [Proposal][R...

...at apple.com>; Hal Finkel > <hfinkel at anl.gov <mailto:hfinkel at anl.gov>>; Zaks, Ayal > <ayal.zaks at intel.com <mailto:ayal.zaks at intel.com>>; Renato Golin > <renato.golin at linaro.org <mailto:renato.golin at linaro.org>>; > mkuper at google.com <mailto:mkuper at google.com>; Mehdi Amini > <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>>; llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > *Subject:* RE: [llvm-dev] [Proposal][RFC] Epilog...

...3.9) on an x86-64 ( both AMD and > Intel ). > > > > -dibyendu > > > > *From:* Matthew Simpson [mailto:mssimpso at codeaurora.org] > *Sent:* Wednesday, December 14, 2016 10:03 PM > *To:* Das, Dibyendu <Dibyendu.Das at amd.com> > *Cc:* Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org > > *Subject:* Re: [llvm-dev] Enabling scalarized conditional stores in the > loop vectorizer > > > > Hi Dibyendu, > > > > Are you using a recent compiler? What architecture are you targeting? The > target will determ...

...ilto:anemet at apple.com] Sent: Tuesday, February 28, 2017 1:33 AM To: Hal Finkel <hfinkel at anl.gov> Cc: Daniel Berlin <dberlin at dberlin.org>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; Zaks, Ayal <ayal.zaks at intel.com>; Renato Golin <renato.golin at linaro.org>; mkuper at google.com; Mehdi Amini <mehdi.amini at apple.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] [Proposal][RFC] Epilog loop vectorization On Feb 27, 2017, at 12:01 PM, Hal Finkel <hfinkel at anl.gov<mailto:hfinkel at anl.gov>> wrote: On 02/27/2017 01...

...t;> <hfinkel at anl.gov <mailto:hfinkel at anl.gov>>; Zaks, Ayal >> <ayal.zaks at intel.com <mailto:ayal.zaks at intel.com>>; Renato >> Golin <renato.golin at linaro.org >> <mailto:renato.golin at linaro.org>>; mkuper at google.com >> <mailto:mkuper at google.com>; Mehdi Amini >> <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>>; >> llvm-dev <llvm-dev at lists.llvm.org >> <mailto:llvm-dev at lists.llvm.org>> >>...

...the load/store plus shuffle sequences > that the vectorizer generates to target-specific instrinsics. > > > > -- Matt > > > > > > *From:* Nema, Ashutosh [mailto:Ashutosh.Nema at amd.com] > *Sent:* Friday, August 05, 2016 7:21 AM > *To:* Michael Kuperstein <mkuper at google.com>; Demikhovsky, Elena < > elena.demikhovsky at intel.com> > *Cc:* Renato Golin <renato.golin at linaro.org>; Sanjay Patel < > spatel at rotateright.com>; Matthew Simpson <mssimpso at codeaurora.org>; > llvm-dev <llvm-dev at lists.llvm.org> &...

Hi Matt- Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and Intel ). -dibyendu From: Matthew Simpson [mailto:mssimpso at codeaurora.org] Sent: Wednesday, December 14, 2016 10:03 PM To: Das, Dibyendu <Dibyendu.Das at amd.com> Cc: Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Enabling scalarized conditional stores in the loop vectorizer Hi Dibyendu, Are you using a recent compiler? What architecture are you targeting? The target will determine whether the vectorizer thinks vectorization is profitabl...

Hi Michael, > On Jan 13, 2017, at 6:38 PM, Michael Kuperstein <mkuper at google.com> wrote: > > As a person not developing on GlobalISel, I can already play with it by setting the flag. ;-) > > The main (and huge) benefit I see is that it will get tested by default. I agree. > So, I think it's mainly a question of maturity - if my (non-Globa...

...________________ From: Graham Hunter <Graham.Hunter at arm.com> Sent: 28 May 2019 10:46 To: JinGu Kang Cc: Joel Jones; Chris Lattner; Hal Finkel; Jones, Joel; dag at cray.com; Renato Golin; Kristof Beyls; Amara Emerson; Florian Hahn; Sander De Smalen; Robin Kruppe; llvm-dev at lists.llvm.org; mkuper at google.com; Sjoerd Meijer; Sam Parker; nd Subject: Re: [EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths Hi JinGu, > Above vectorized loop does not need tail loop. I guess we could map the %mask.vec to predicate register as native register class on ISelLower...

...reg->node[i].state ^= ((unsigned int)1 << target); > > } > > } > > *From:* llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] *On Behalf Of *Matthew > Simpson via llvm-dev > *Sent:* Tuesday, December 13, 2016 7:12 PM > *To:* Michael Kuperstein <mkuper at google.com> > *Cc:* llvm-dev <llvm-dev at lists.llvm.org> > *Subject:* Re: [llvm-dev] Enabling scalarized conditional stores in the > loop vectorizer > > > > Hi Michael, > > > > Thanks for testing this on your benchmarks and target. I think the results &...

..., |Hal | |----- Original Message ----- |> From: "Elena Demikhovsky" <elena.demikhovsky at intel.com> |> To: "llvm-dev" <llvm-dev at lists.llvm.org> |> Cc: "Ayal Zaks" <ayal.zaks at intel.com>, "Michael Kuperstein" |<mkuper at google.com>, "Adam Nemet (anemet at apple.com)" |> <anemet at apple.com>, "Hal Finkel (hfinkel at anl.gov)" |<hfinkel at anl.gov>, "Sanjay Patel (spatel at rotateright.com)" |> <spatel at rotateright.com>, "Nadav Rotem" |...

...essage ----- |> |> From: "Elena Demikhovsky" <elena.demikhovsky at intel.com> |> |> To: "llvm-dev" <llvm-dev at lists.llvm.org> |> |> Cc: "Ayal Zaks" <ayal.zaks at intel.com>, "Michael Kuperstein" |> |<mkuper at google.com>, "Adam Nemet (anemet at apple.com)" |> |> <anemet at apple.com>, "Hal Finkel (hfinkel at anl.gov)" |> |<hfinkel at anl.gov>, "Sanjay Patel (spatel at rotateright.com)" |> |> <spatel at rotateright.com>, &qu...