search for: misalign

...timeLLVMfft.s I got the errors at the bottom of this email in response to the last command. On the other hand, gcc v2.95.3 had no problem compiling this code. Any idea what's wrong? Thanks, - Nick -- /opt/SUNWspro/bin/../SC5.0/bin/fbe: "timeLLVMfft.s", line 3579: error: invalid (misaligned) register /opt/SUNWspro/bin/../SC5.0/bin/fbe: "timeLLVMfft.s", line 3580: warning: not even-numbered register /opt/SUNWspro/bin/../SC5.0/bin/fbe: "timeLLVMfft.s", line 3598: warning: not even-numbered register /opt/SUNWspro/bin/../SC5.0/bin/fbe: "timeLLVMfft.s", line...

https://bugs.freedesktop.org/show_bug.cgi?id=27680 Summary: Misaligned reg ... nVidia Corporation C67 [GeForce 7150M / nForce 630M] (rev a2) Product: xorg Version: git Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: major Priority: medium Compo...

Thanks to Jakob's work on Sparcv9 ABI in Clang and recent changes to Sparc code generator, I am happy to announce that Clang can self host itself on Linux/Sparc64 and on FreeBSD/Sparc64. However, it still fails on a few unit tests and nightly tests, primarily due to misaligned memory accesses in the code (See bugs 18482, 18500, 18502, 18536, 18693). Unlike other architectures, misaligned loads/stores cause bus errors in Sparc. To catch bugs specific to Sparc such as the misalignment bugs, it would be great to get some buildbots running on Sparc machines. I see that th...

...urrent machine (x86_64) the cpu doesn't seem to care, but I suspect this isn't true on all platforms (not is true on this platform if I do atomic operations). Yet the pointer for this i32 which I get is the same as a normal i32 pointer. Is there supposed to be a special marker for possibly misaligned pointers? Or how I am supposed to track such misaligned pointers and ensure they aren't used incorrectly? -- edA-qa mort-ora-y -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Sign: Please digitally sign your emails. Encrypt: I'm also happy to receive encrypted m...

http://bugs.freedesktop.org/show_bug.cgi?id=24295 Summary: No Boot With Nouveau DRM - C51 misaligned reg 0x0000#### not verified Product: xorg Version: unspecified Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: critical Priority: highest Component: Driver/nouveau A...

https://bugs.freedesktop.org/show_bug.cgi?id=47182 Bug #: 47182 Summary: GeFroce 6150SE nForce 430: misaligned reg 0x0060081D Classification: Unclassified Product: xorg Version: 7.6 (2010.12) Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau Assign...

This maybe a basic question, but I have spent several hours researching and I could not get an answer, so please bear with me. The problem is with time series in the package tseries. As the example below shows, the time series can get misaligned, so that bad results are obtained when doing regressions. I found a way to do this correctly, but I find it rather cumbersome. My question is: is there a better way to do it? Thanks for any help. Suppose I define: > y1<-ts(c(1,2,3,5,7)) > x1<-diff(y1) > z1<-ts(c(1,1,2,2)) Th...

On Thu, Nov 10, 2011 at 6:13 PM, Aaron Dwyer <Aaron.Dwyer at imgtec.com> wrote: > Using LLVM 2.9, the following LLVM IR produces invalid x86 32 bit assembly > (a misaligned SSE store). > ; ModuleID = 'MisalignedStore' > define void @MisalignedStore() nounwind readnone { > entry: >   %v = alloca <4 x float>, align 16 >   store <4 x float> zeroinitializer, <4 x float>* %v, align 16 >   br label %post-block > post-block: &...

Using LLVM 2.9, the following LLVM IR produces invalid x86 32 bit assembly (a misaligned SSE store). ; ModuleID = 'MisalignedStore' define void @MisalignedStore() nounwind readnone { entry: %v = alloca <4 x float>, align 16 store <4 x float> zeroinitializer, <4 x float>* %v, align 16 br label %post-block post-block: %f = alloca float ret void }...

...the > cpu doesn't seem to care, but I suspect this isn't true on all platforms > (not is true on this platform if I do atomic operations). Yet the > pointer for this i32 which I get is the same as a normal i32 pointer. > > Is there supposed to be a special marker for possibly misaligned > pointers? Or how I am supposed to track such misaligned pointers and > ensure they aren't used incorrectly? in LLVM, pointer types don't have an alignment associated with them. Instead it is pointer operations that have an alignment (when relevant), for example load and store ins...

Hi, NetApp support has suggested us aligning partitions to improve performance, in short: starting sector must be divisible by 8. How can I move the start point in a misaligned partition -in production, with ext3- under Linux? A screenshot with a misaligned (start=63s) and aligned (start=64s) partition is available at: http://filesocial.com/lkwvvn2 (If anyone is interested in this topic, NetApp has a good document explaining performance issues in misaligned parti...

...#39;s work on Sparcv9 ABI in Clang and recent changes to >> Sparc code generator, I am happy to announce that Clang can self host >> itself on Linux/Sparc64 and on FreeBSD/Sparc64. >> >> However, it still fails on a few unit tests and nightly tests, >> primarily due to misaligned memory accesses in the code (See bugs >> 18482, 18500, 18502, 18536, 18693). Unlike other architectures, >> misaligned loads/stores cause bus errors in Sparc. >> >> To catch bugs specific to Sparc such as the misalignment bugs, it >> would be great to get some buildb...

Am 22.04.2016 um 12:40 schrieb g <geleem at bellsouth.net>: > greetings. > > centos 6.7 [current] > > > 'disk utility' has started showing message; > > WARNING: The partition is misaligned by 2560 bytes. This may > result in very poor performance. Repartitioning is suggested. > > for sdc5 - /home partition. > > /dev/sdc5 302243312 156348604 130534968 55% /home > /dev/sdc7 80854912 57088 76683952 1% /hdd/c/07 > > other than time invol...

> I've seen the exact same in my version (mingw on win32), and the problem > was that the stack was misaligned when entering the function, so the temp > registers weren't at 16-byte boundries. That's a possibility. It's easy to check by printing the address of the variables. I know that gcc 3.3 had some alignment issues with _m128 that were supposed to be fixed in version 3.4 and above....

Hello, I recently noticed a small bug in the doveadm table formatter: hidden titles may cause the headers to be misaligned. The behavior in question was introduced by commit <http://hg.dovecot.org/dovecot-2.2/rev/210282ae46e1> and doveadm -f table quota get -A may be used to reproduce it. Most simple patch attached: it simply restores the old behavior, to some extent. Actually hiding those titles may be desi...

An NA in the rownames of a matrix (or dataframe) causes misalignment when the matrix is printed: R> x <- matrix(1:12, 3,4, dimnames=list(letters[1:3], LETTERS[1:4])) R> rownames(x)[2] <- NA R> x A B C D a 1 4 7 10 <NA> 2 5 8 11 c 3 6 9 12 The bug is in function Rstrlen, in src/main/printutils.c. MatrixRowLabel and MatrixColu...

...data <-subset(df,select=c(proportion_1,proportion_2,proportion_3)) prop.tab <- as.table(as.matrix(prop.data)) barchart.obj<-barchart(prop.tab, stack=TRUE, horizontal = FALSE) #Second, generate the dots of outcome (I could have used type="l" but using type="p" makes the #misalignment of x-axis more obvious. dot.outcome <- xyplot(outcome~group,df,type="p", col="blue") #Last, overlay the two plots barchart.obj+ as.layer(dot.outcome,style=2,axes=c("y"), outside=TRUE) #Now, you should be able to see the x-axis of the two plots are not matching....

...ndle wideband for speex wideband? ii) does it handle feedback or howling? Lastly, a newbie question for echo cancellation: is there a convenient test to ensure that the input and output buffers obtained from the audio IO are aligned? and also, does anyone have any rough idea what is the tolerated misalignment of the input and output buffers, assuming constant misalignment thanks in advance, tk -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.xiph.org/pipermail/speex-dev/attachments/20051221/97c191da/attachment.html

...is indeed related to this Connex back end that it's not yet part of the LLVM source repository - an important thing proposed in the project is that we plan to perform efficient realignment for this Connex vector processor. I looked a bit in LLVM and I see that support for realignment of misaligned vector memory accesses is not implemented in the LoopVectorize pass (see lib/Transforms/Vectorize/LoadStoreVectorizer.cpp) nor in any back end (folder lib/Target). Please correct me if I'm wrong. But realignment is an interesting technique useful for many SIMD and (wide) vector proce...

...> %4) ret void } declare arm_aapcscc void @bugtest(<2 x i8> %c, <2 x i8> %uc) and expect first parameter to be passed into a single 32-bit register. using llc -mcpu=cortex-a9 -mattr=+neon With LLVM 3.0 %c is passed into two 32-bit regs and code works. With LLVM 3.1 it generate a misaligned load that cause a BUS error seems linked to promote element optimization. With LLVM trunk it generates a misaligned load that makes the assembler fail. I guess that to avoid such problem I need to convert small vector parameters into i32, right ? Thanks for your answers Best Regards Seb