Displaying 7 results from an estimated 7 matches for "mipsisd".
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2012 Oct 06
2
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...ExtractElementF64 in mips. I added the following Code to InstrFPU.td (and
added the CopyF64 ISD to another file):
def SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>,
SDTCisVT<1, f64>]>;
def MipsCopyF64 : SDNode<"MIPSISD::CopyF64",
SDT_MIPSCopyF64>;
I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired register class)
in the DMFC1 rule for testing.
Next, I added the code in ExpandPseudo to use the following pseudo
instruction expansion:
void MipsExpandPseudo::Ex...
2012 Oct 09
0
[LLVMdev] Pairing Registers on a Target Similar to Mips?
...I added the following Code to InstrFPU.td (and
> added the CopyF64 ISD to another file):
>
> def SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>,
> SDTCisVT<1, f64>]>;
>
> def MipsCopyF64 : SDNode<"MIPSISD::CopyF64",
> SDT_MIPSCopyF64>;
>
> I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired register class)
> in the DMFC1 rule for testing.
>
> Next, I added the code in ExpandPseudo to use the following pseudo
> instruction expansio...
2011 Jun 22
1
[LLVMdev] Mips backend -- Incorrect globaladdr/constpool address generation when bit 15 of address is set?
...d the lower address part in
// the instruction itself. Example, instead of:
// lui $2, %hi($CPI1_0)
// addiu $2, $2, %lo($CPI1_0)
// lwc1 $f0, 0($2)
// Generate:
// lui $2, %hi($CPI1_0)
// lwc1 $f0, %lo($CPI1_0)($2)
if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
SDValue LoVal = Addr.getOperand(1);
if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
Base = Addr.getOperand(0);
Offset = L...
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
...alAddress has number 5
-Operation GlobalAddress has number 6
-Operation TargetConstant has number 7
-Operation callseq_start has number 8
-Operation TargetGlobalAddress has number 9
-Operation Register has number 10
-Operation CopyToReg has number 11
-Operation RegisterMask has number 12
-Operation MipsISD::JmpLink has number 13
-Operation TargetConstant has number 14
-Operation TargetConstant has number 15
-Operation callseq_end has number 16
-Operation Register has number 17
-Operation CopyFromReg has number 18
-Operation CopyToReg has number 19
-Operation Register has number 20
-Operation MipsISD:...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...0x88c8eb0: <multiple use>
0x88c8b08: ch,flag = CopyToReg 0x88ca410, 0x88ca478, 0x88c8eb0
0x88c8b08: <multiple use>
0x88ca1e8: i32 = TargetGlobalAddress <i32 (i8*)* @atoi> 0
0x88ca478: <multiple use>
0x88c8b08: <multiple use>
0x88c8b80: ch,flag = MipsISD::JmpLink 0x88c8b08, 0x88ca1e8, 0x88ca478, 0x88c8b08:1
0x88c8b80: <multiple use>
0x88c8810: <multiple use>
0x88c8b80: <multiple use>
0x88c8bd8: ch,flag = callseq_end 0x88c8b80, 0x88c8810, 0x88c8b80:1
0x88c8bd8: <multiple use>
0x88c8cf0: i32 = Register 2...
2018 Sep 01
3
Clang for the PlayStation 2
Hello,
I'm part of the (sadly fairly small) community of PS2 hackers. The current
cross-toolchain for the PS2 is based on GCC 3.2.3, an outdated and buggy
compiler, which I have personally gotten tired of working with, so I would
like to port Clang as a newer cross-compiler for the PS2.
However, the PS2 has some notable quirks which make this a non-trivial task
for the current compiler. It
2012 Jan 19
0
[LLVMdev] Problem generating <target>GenAsmMatcher.inc
...m, 0x1e, "ddiv", IIIdiv>;
Here is the sequence of definitions:
def SDT_MipsDivRem : SDTypeProfile<0, 2,
[SDTCisInt<0>,
SDTCisSameAs<0, 1>]>;
def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
[SDNPOutGlue]>;
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
RegisterClass RC, list<Register> DefRegs>:
FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm,...