search for: mipsgenregisterinfo

...lo, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here. Thanks, Jafar J. -------------- next part ------...

...Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here. Thanks, Jafar J. _________________________...

...physical numbering of each register, to finally generate the complete 32-bit encoding. MachineInstr::getOpcode() for a register operand returns an enum value that doesn’t represent the actual physical numbering of the register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitte...

...> Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here. > > Thanks, > Jafar J. > __________...

...>> Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet generated when I’m trying to include it in the PostRAScheduler. Is this the way to activate the mipsCodeEmitter during PostRA Scheduler or am I missing something here. >> >> Thanks, >> Jafar J. &gt...

...mbering of each register, to finally generate the complete 32-bit encoding. > > MachineInstr::getOpcode() for a register operand returns an enum value that doesn’t represent the actual physical numbering of the register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. > > However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the...

...ysical numbering of each register, to finally generate the complete 32-bit encoding. MachineInstr::getOpcode() for a register operand returns an enum value that doesn’t represent the actual physical numbering of the register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emit...

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

...of each register, to finally generate the complete 32-bit encoding. >> >> MachineInstr::getOpcode() for a register operand returns an enum value that doesn’t represent the actual physical numbering of the register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. >> >> However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activat...

What is the purpose of tablegen created files for fast-isel? If I make the following change to Makefile in lib/Target/Mips BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ MipsGenAsmWriter.inc MipsGenCodeEmitter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ - MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ + MipsGenSubtargetInfo.inc MipsGenFastISel.inc MipsGenMCCodeEm...

Thanks for your reply Quentin. I do understand that the registers are allocated much later in the pipeline. I am assuming that the physical registers are allocated before MipsAsmPrinter class. I am doing something like if (MI->getOpcode() == Mips::OPCODE) { unsigned n = MI->getNumOperands(); for(unsigned i=0 ; i < n ; i++) { const MachineOperand &MO =

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? For the Mips platform we create the following .inc files through tblgen. tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter) tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel) tablege...

...Parser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create the following .inc files through tblgen. > > tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) > tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) > tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter) > tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter) > tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer) > tablegen(LLVM MipsGenDAGISel.i...

> On Feb 27, 2015, at 1:59 AM, Ambuj Agrawal <ambujbwt at gmail.com> wrote: > > Is it possible to get a register number to which the value is allocated to in MIPS in DAGToDAG class? > > More Specifically: > SDValue Reg3 = Node->getOperand(3); > if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Reg3)) >

...dev/null +++ b/lib/Target/Mips/.gitignore @@ -0,0 +1,12 @@ +MipsGenAsmMatcher.inc +MipsGenAsmWriter.inc +MipsGenCallingConv.inc +MipsGenCodeEmitter.inc +MipsGenDAGISel.inc +MipsGenDisassemblerTables.inc +MipsGenEDInfo.inc +MipsGenInstrInfo.inc +MipsGenMCCodeEmitter.inc +MipsGenMCPseudoLowering.inc +MipsGenRegisterInfo.inc +MipsGenSubtargetInfo.inc diff --git a/lib/Target/NVPTX/.gitignore b/lib/Target/NVPTX/.gitignore new file mode 100644 index 0000000..74001d1 --- /dev/null +++ b/lib/Target/NVPTX/.gitignore @@ -0,0 +1,5 @@ +NVPTXGenAsmWriter.inc +NVPTXGenDAGISel.inc +NVPTXGenInstrInfo.inc +NVPTXGenRegisterInfo.i...