search for: mipsasmparser

I would like to make the following member of AsmPrinter be protected void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT) const; I have some stubs that I want to emit in MipsAsmParser . Are there any objections to doing this? Reed

...rinter be protected >> >> >> void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, >> InlineAsm::AsmDialect AsmDialect = >> InlineAsm::AD_ATT) const; >> >> I have some stubs that I want to emit in MipsAsmParser . >> >> Are there any objections to doing this? >> >> Reed >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listin...

...g to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have seen that in Target.td file in class instruction there is a flag isAsmParserOnly...

I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? For the Mips platform we create the following .inc files through tblgen. tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) tablegen(LLVM Mips...

Hi ES, From what I understand instruction parsing is divided into two parts: - Parsing an operand list (XXXAsmParser::ParseInstruction) - Turning the operand list into an actual instruction (XXXAsmParser::MatchAndEmitInstruction) The second part does the validation (e.g. how many operands, what kind, etc) while the first part only does the parsing. That's why I think in the first part

...z inline asm operand modifier with non-immediates. * r216262 - [mips] Don't use odd-numbered float registers for double arguments for fastcc calling convention if FP is 64-bit and +nooddspreg is used. * r217257 - [mips] Change Feature-related types from unsigned to uint64_t in MipsAsmParser. No functional changes. * r218745 - [mips] Fix disassembly of [ls][wd]c[23], cache, and pref I'd also like to propose the inclusion of the recent ABI fixes to the Mips target but I'm not sure this is a good idea. I'm having difficulty sorting out the dependencies for these at...

I'm trying to build a standalone assembler for Mips using AsmParser. Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. I am getting an assertion for what I believe are multiple register definitions with the same name. llvm-tblgen: /home/jcarter/workarea/asm/llvm/utils/TableGen/StringMatcher.cpp:52: bool llvm::StringMatcher::EmitStringMatcherForChar(const std::vect...

Hi, On Instructions you can use checkEarlyTargetMatchPredicate() to check that the operands are the same. There's an example of that in MipsAsmParser.cpp for DATI and DAHI. I can't think of a reason TableGen couldn't be made to allow this for InstAlias too. > On 15 Dec 2017, at 02:12, via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hello, > > InstAlias does not allow tied operands (repeated operands) in the a...

Hello, InstAlias does not allow tied operands (repeated operands) in the asm string to be matched. It seems this situation is explicitly prevented in AsmMatcherEmitter.cpp: if (!Hack) PrintFatalError(TheDef->getLoc(), "ERROR: matchable with tied operand '" + Tok + "' can never be matched!");

...g to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have seen that in Target.td file in class instruction there is a flag isAsmParserOnly...

...umbered float registers for double > arguments for fastcc calling convention if FP is 64-bit and +nooddspreg is > used. > > > > This all look OK to me, go ahead an merge. Thanks. > > * r217257 - [mips] Change Feature-related types from unsigned to > uint64_t in MipsAsmParser. No functional changes. > > > > I'm a little concerned this might break the shared library ABI. We will need > to verify that it doesn't before it gets merged. I don't think this will break it since the two functions that are changed are private to MipsAsmParser and ou...

Hi Jack, On Jan 25, 2012, at 6:45 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to generate MipsGenAsmMatcher.inc for MipsAsmParser.cpp. > > What added restrictions for the .td file contents are there for tblgen -gen-asm-matcher? > Lots, as you're finding, almost all of them completely undocumented. :( > For the Mips platform we create the following .inc files through tblgen. > > tablegen(LLVM MipsGe...

...r be protected > > > > > > void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, > > InlineAsm::AsmDialect AsmDialect = > > InlineAsm::AD_ATT) const; > > > > I have some stubs that I want to emit in MipsAsmParser . > > You mean Printer? There is no such a thing as inline asm in a .s file. > > > Are there any objections to doing this? > > Probably. EmitInilneAsm is the only case I know that has a reasonable use of > hasRawTextSupport in order for it to work on targets without an as...

...g to solve a problem regarding complex macro instructions. As mips assembler supports macro instructions that can develop to more then one real instruction depending on the operand type(usually two or three) we can't use InstAlias to exploit tableGen generated code. Currently we expand these in MipsAsmParser in a post processing methods, but I would like to at least be able to easily identify them, and if possible call some method that handles this to avoid giant switch/case structure in method that processes them. I have seen that in Target.td file in class instruction there is a flag isAsmParserOnly...

> > > > I'd also like to propose the inclusion of the recent ABI fixes to the Mips > > > > target but I'm not sure this is a good idea. I'm having difficulty sorting out the > > > > dependencies for these at the moment since they seem to depend on some > > > > of Eric Christopher's Subtarget/TargetMachine refactoring. It may also be a

On Jan 31, 2012, at 1:26 PM, Carter, Jack wrote: > I'm trying to build a standalone assembler for Mips using AsmParser. > > Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. > > I am getting an assertion for what I believe are multiple register definitions with the same name. > > llvm-tblgen: /home/jcarter/workarea/asm/llvm/utils/TableGen/StringMatcher.cpp:52: bool llvm::StringMatcher::EmitStringMatcherFor...

...at 1:26 PM, "Carter, Jack" <jcarter at mips.com> wrote: > I'm trying to build a standalone assembler for Mips using AsmParser. > > Following the lead of X86, ARM and MBlaze I have run tblgen -gen-asm-matcher on Mips.td to produce tables and methods to aid the parser (MipsAsmParser.cpp) which is a stripped down ARM implementation. > > I am getting an assertion for what I believe are multiple register definitions with the same name. > > llvm-tblgen: /home/jcarter/workarea/asm/llvm/utils/TableGen/StringMatcher.cpp:52: bool llvm::StringMatcher::EmitStringMatcherFor...

...rinter be protected >> >> >> void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0, >> InlineAsm::AsmDialect AsmDialect = >> InlineAsm::AD_ATT) const; >> >> I have some stubs that I want to emit in MipsAsmParser . > You mean Printer? There is no such a thing as inline asm in a .s file. > >> Are there any objections to doing this? > Probably. EmitInilneAsm is the only case I know that has a reasonable > use of hasRawTextSupport in order for it to work on targets without an > asm parser....

...validate(CommentDelimiter, true); Matchables.push_back(std::move(II)); } On 2017-12-15 03:40, Daniel Sanders wrote: > Hi, > > On Instructions you can use checkEarlyTargetMatchPredicate() to check > that the operands are the same. There's an example of that in > MipsAsmParser.cpp for DATI and DAHI. I can't think of a reason > TableGen couldn't be made to allow this for InstAlias too. > >> On 15 Dec 2017, at 02:12, via llvm-dev <llvm-dev at lists.llvm.org> >> wrote: >> >> Hello, >> >> InstAlias does not allow ti...

On Apr 8, 2013, at 2:55 PM, "Robinson, Paul" <Paul_Robinson at playstation.sony.com> wrote: I keep seeing "this is a layering violation" comments on the lists. > While there are a few llvm.org pages that mention layers in passing, > there is nothing (that I've found) actually specifying the layers. > Trying to infer the layering from the code is tedious and