search for: microoper

Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM

> On Sep 22, 2017, at 10:34 AM, Thorsten Schütt via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: > name LDADDALX; class 872 > microops 65535 > I would have assumed that the microops are less than

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on:

> On May 9, 2018, at 9:43 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi, > > I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. > Are we modeling the decoder phase or the execution stage? > > Background: > > First of all, there seems to be different meanings of

On Fri, Sep 29, 2017 at 7:51 PM, Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > > On Sep 22, 2017, at 10:34 AM, Thorsten Schütt via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > > > > #define GET_REGINFO_ENUM > > #include "AArch64GenRegisterInfo.inc" > > > > #define GET_INSTRINFO_ENUM >

On Thu, Mar 26, 2015 at 11:50:20PM -0700, Andrew Trick wrote: > > > On Mar 26, 2015, at 7:36 PM, Tom Stellard <tom at stellard.net> wrote: > > > > Hi, > > > > I have a program with over 100 loads (each with a 10 cycle latency) > > at the beginning of the program, and I can't figure out how to get > > the machine scheduler to intermix ALU

On Oct 21, 2011, at 12:15 AM, James Molloy wrote: > Hi Andy, > > Could you describe how this would be done? In the current ARM itineraries > (say C-A9 for example), the superscalar issue stage is modelled as taking 1 > cycle. If it were to take 2 cycles instead, as far as I can tell the hazard > analyser would stall because both FU's would be acquired. > > I would

> On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named llvm-mca. We > currently use it internally to statically measure the performance of code, and > to help triage potential problems with target scheduling models. We decided to > post this RFC because

Hi Andrew, Thanks for the feedback! On Fri, Mar 2, 2018 at 1:16 AM, Andrew Trick <atrick at apple.com> wrote: > > On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named > llvm-mca. We > currently use it internally to statically measure the

Hi all, At Sony we developed an LLVM based performance analysis tool named llvm-mca. We currently use it internally to statically measure the performance of code, and to help triage potential problems with target scheduling models. We decided to post this RFC because we are interested in the feedback from the community, and we also believe that other people might be interested in a tool like