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Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM #include "AArch64GenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "AArch64Ge...

...10:34 AM, Thorsten Schütt via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: > name LDADDALX; class 872 > microops 65535 > I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? > > Cheers, > Tom > > #define GET_REGINFO_ENUM > #include "AArch64GenRegisterInfo.inc" > > #define...

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on: https://stackoverflow.com/questions/23...

> On May 9, 2018, at 9:43 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi, > > I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. > Are we modeling the decoder phase or the execution stage? > > Background: > > First of all, there seems to be different meanings of "issue" depending on which platform you're on: > > https...

...h64MCInstrInfo(&II); > > > > llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX); > > llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX); > > > > printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass); > > > > printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d. > SchedClass)->NumMicroOps); > > > > return 0; > > } > > > > /* > > LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum > > */ > > I bet the problem is that “WriteAtomic” is marked...

On Thu, Mar 26, 2015 at 11:50:20PM -0700, Andrew Trick wrote: > > > On Mar 26, 2015, at 7:36 PM, Tom Stellard <tom at stellard.net> wrote: > > > > Hi, > > > > I have a program with over 100 loads (each with a 10 cycle latency) > > at the beginning of the program, and I can't figure out how to get > > the machine scheduler to intermix ALU

...tional units at different pipeline stages. If I have an instruction that consumes a functional unit for 2 cycles, during which no other instruction may be issued to that unit, then I need to do this: [InstrStage<2, [NonPipelinedUnit]> If I have an instruction that splits into two dependent microops, that use the same type of functional unit, but at different times, then I need to do this: [InstrStage<1, [ALU0, ALU1], 1> InstrStage<1, [ALU0, ALU1]> -Andy >From TargetScheduled.td: //===----------------------------------------------------------------------===// // Instruction...

...ine independent way, and half the world seems to swap the meaning of those terms. If you’re going to make this distinction please define the terms clearly in the machine model and explain how tools are expected to use the information. Currently IssueWidth is used to tell the scheduler that ’N' microops will definitely take ’N’ / ‘IssueWidth’ cycles regardless of which functional units or dispatch pipeline is involved. [Reading below, I saw that you define instruction “dispatch" as what the LLVM machine model calls “issue”. LLVM doesn’t model dispatch directly because, by its definition, it...

...> half the world seems to swap the meaning of those terms. If you’re going to > make this distinction please define the terms clearly in the machine model > and explain how tools are expected to use the information. > > Currently IssueWidth is used to tell the scheduler that ’N' microops will > definitely take ’N’ / ‘IssueWidth’ cycles regardless of which functional > units or dispatch pipeline is involved. > > [Reading below, I saw that you define instruction “dispatch" as what the > LLVM machine model calls “issue”. LLVM doesn’t model dispatch directly > be...

Hi all, At Sony we developed an LLVM based performance analysis tool named llvm-mca. We currently use it internally to statically measure the performance of code, and to help triage potential problems with target scheduling models. We decided to post this RFC because we are interested in the feedback from the community, and we also believe that other people might be interested in a tool like