search for: microop

Hi all, I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: name LDADDALX; class 872 microops 65535 I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? Cheers, Tom #define GET_REGINFO_ENUM #include "AArch64GenRegisterInfo.inc" #define GET_INSTRINFO_ENUM #include "AArch64G...

...10:34 AM, Thorsten Schütt via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi all, > > I am looking at the scheduling model of the ThunderX2. I am trying to figure out the cost of the LDADDALX instruction. The following program’s output is: > name LDADDALX; class 872 > microops 65535 > I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong? > > Cheers, > Tom > > #define GET_REGINFO_ENUM > #include "AArch64GenRegisterInfo.inc" > > #defin...

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on: https://stackoverflow.com/questions/2...

> On May 9, 2018, at 9:43 AM, Jonas Paulsson <paulsson at linux.vnet.ibm.com> wrote: > > Hi, > > I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. > Are we modeling the decoder phase or the execution stage? > > Background: > > First of all, there seems to be different meanings of "issue" depending on which platform you're on: > > http...

...h64MCInstrInfo(&II); > > > > llvm::StringRef ref = II.getName(llvm::AArch64::LDADDALX); > > llvm::MCInstrDesc d = II.get(llvm::AArch64::LDADDALX); > > > > printf("name %s; class %d\n", ref.str().c_str(), d.SchedClass); > > > > printf("microops %d\n", llvm::ThunderX2T99Model.getSchedClassDesc(d. > SchedClass)->NumMicroOps); > > > > return 0; > > } > > > > /* > > LDADDALB_LDADDALH_LDADDALW_LDADDALX = 872, in Sched enum > > */ > > I bet the problem is that “WriteAtomic” is marke...

On Thu, Mar 26, 2015 at 11:50:20PM -0700, Andrew Trick wrote: > > > On Mar 26, 2015, at 7:36 PM, Tom Stellard <tom at stellard.net> wrote: > > > > Hi, > > > > I have a program with over 100 loads (each with a 10 cycle latency) > > at the beginning of the program, and I can't figure out how to get > > the machine scheduler to intermix ALU

...tional units at different pipeline stages. If I have an instruction that consumes a functional unit for 2 cycles, during which no other instruction may be issued to that unit, then I need to do this: [InstrStage<2, [NonPipelinedUnit]> If I have an instruction that splits into two dependent microops, that use the same type of functional unit, but at different times, then I need to do this: [InstrStage<1, [ALU0, ALU1], 1> InstrStage<1, [ALU0, ALU1]> -Andy >From TargetScheduled.td: //===----------------------------------------------------------------------===// // Instruction...

...er detail, but the benefit didn’t justify the complexity and compile time. I always felt that a static analysis tool was the right place for this kind of simulation. > A few examples of details that are missing in scheduling models are: > - Maximum number of instructions retired per cycle. MicroOpBufferSize is presumed to cover register renaming and retirement, assuming they are well-balanced. For your tool, you certainly want to be more precise. > - Actual dispatch width (it often differs from the issue width). This was always a hard one to generalize in a machine independent way, and...

...s tool was the right place for this kind of simulation. > I agree. I am pretty confident that all the extra details can become opt-in for targets. > A few examples of details that are missing in scheduling models are: > - Maximum number of instructions retired per cycle. > > > MicroOpBufferSize is presumed to cover register renaming and retirement, > assuming they are well-balanced. For your tool, you certainly want to be > more precise. > Yes. The long term goal is to have specific (optional) fields for targets that want to specify a different value. MicroOpBufferSize...

...ng how many temporaries are available for register renaming, the tool can predict dispatch stalls caused by the lack of temporaries. The number of reorder buffer entries consumed by an instruction depends on the number of micro-opcodes it specifies in the target scheduling model (see field 'NumMicroOpcodes' of tablegen class ProcWriteResources and its derived classes; TargetSchedule.td). The reorder buffer is implemented by class RetireControlUnit (see Dispatch.h). Its goal is to track the progress of instructions that are "in-flight", and retire instructions in program order. Th...