search for: mi3

...I1), (isScalarType type:$D), (isLargerType type:$D, type:$S)), (apply (G_ZEXT $D, $S, (debug_locations $MI0, $MI1)))>; def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1, (DBG_VALUE $t0):$MI2, (DBG_VALUE $D):$MI3, (isScalarType type:$D),...

..._ZEXT $t0, $S):$MI0, >> (G_TRUNC $D, $t0):$MI1), >> (isScalarType type:$D), >> (isLargerType type:$D, type:$S)), >> (apply (G_ZEXT $D, $S, (debug_locations $MI0, $MI1)))>; >> def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), >> (match (G_ZEXT $t0, $S):$MI0, >> (G_TRUNC $D, $t0):$MI1, >> (DBG_VALUE $t0):$MI2, >> (DBG_VALUE $D):$MI3, >>...

...nstance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> // Use the lo subreg that was setup in MI1: .... .... MI4:: %vreg32<def> = COPY %vreg7; //Not trivial because 7 is not killed. This is the Copy C i.e. B1=A3. .... MI5:: Conditional...

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

...ot;LM3", "DB1" ,"DB2" ,"DB3", "DM1" , "DM2" , "DM3" , "FI1", "FI2", "BKI1", "BKI2", "BKO1", "BKO2", "BKO3", "SUR1","MI1","MI2","MI3","BHE1","BHE2","BHE3","BHW1","BHW2","BHW3","HAL1","HAL2","HAL3","HAL4","HAL5","HAL6","HAL7","DOH1","DOH2","DOH3","DOH4",&quo...

...ocations $DL0, $DL1)))>; However, the former is more compact when DBG_VALUE is involved since naming the instruction gives access to three of the four pieces of data we need to pass on to the apply step: def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1, instr:$MI2, instr:$MI3, debug_expr:$DNewExpr), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1, (DBG_VALUE $t0):$MI2, (DBG_VALUE $D):$MI3, (isScalarType type:$D),...

...art of a single block loop). > > MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, > 2, // Post Inc. Load. Vreg7 is a 64bit reg. > MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> > // This is the A3 = B0 above. > MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32:subreg_loreg<kill> > // Use the lo subreg that was setup in MI1: > .... > .... > MI4:: %vreg32<def> = COPY %vreg7; //Not trivial > because 7 is not killed. This is the Copy C i.e. B1=A...

> On Nov 10, 2018, at 03:28, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > Thank you for the detailed reply! There's a lot to digest :) Let me try to address most of it. > > > [snip] >>> I also think you should have 'ins' and 'outs' separately; after all, a predicate may have to do a combined check on two matched registers / operands,

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Hello list. I'm trying to rebuild the 2.6.9.67.0.20.EL kernel, but it fails even without modifications. How did I try it? Created a (non-root) build environment (not a mock ) Installed the kernel.scr.rpm and did a rpmbuild -ba --target=`uname -m` kernel-2.6.spec 2> prep-err.log | tee prep-out.log The build failed at the end: Processing files: kernel-xenU-devel-2.6.9-67.0.20.EL Checking