search for: mfp64

...egisters def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; /// Mips Double point precision FPU Registers (aliased /// with the single precision to hold 64 bit values) def D0 : AFPR< 0, "F0", [F0, F1]>; /// Mips Double point precision FPU Registers in MFP64 mode. def D0_64 : AFPR64<0, "F0", [F0]>; Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen. The examples here are from lib/Target/Mips/MipsRegisterInfo.td. Do I just need to use/write another register parser? Or is there a cle...

...generate objects > that can be used on both a 32-bit and 64-bit FPU. In recent compilers > it is enabled by default. The most likely cause of the warning is some > inline assembly that doesn't obey the small restrictions that FPXX > enforces. Assuming, this is the cause –mfp32/-mfp64 should provide a > work around but I'd recommend updating the inline assembly since this > will make it easier to port to newer Mips processors. > > // Just tested with xercesc v3, got these warnings (sorry I said error message in last reply) > DOMNodeIDMap.s:134: Warning: fl...

..., "F0">, DwarfRegNum<[32]>; > > /// Mips Double point precision FPU Registers (aliased > /// with the single precision to hold 64 bit values) > def D0 : AFPR< 0, "F0", [F0, F1]>; > > /// Mips Double point precision FPU Registers in MFP64 mode. > def D0_64 : AFPR64<0, "F0", [F0]>; > > Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen. > > The examples here are from lib/Target/Mips/MipsRegisterInfo.td. > > Do I just need to use/write another...

...985.s: Assembler messages: /tmp/test-a51985.s:11: Warning: `fp=64' used with a 32-bit ABI /usr/local/bin/mipsel-unknown-linux-gnu-ld: Warning: a.out uses -mdouble-float (set by /opt/toolchain_clang/host/usr/mipsel-unknown-linux-gnu/sysroot/usr/lib/../lib/crt1.o), /tmp/test-d48db1.o uses -mgp32 -mfp64 How can I change the *fp=64* to *fp=32*? Have tried pass -mfp32 to mipsel-unknown-linux-gnu-clang++ but with no luck. Though this is a warning, but it fails to compile Qt. Yes I known it works if uses *-mips64* etc, but I need mips3. Please let me know if I'm post to the wrong...

..., "F0">, DwarfRegNum<[32]>; > > /// Mips Double point precision FPU Registers (aliased > /// with the single precision to hold 64 bit values) > def D0 : AFPR< 0, "F0", [F0, F1]>; > > /// Mips Double point precision FPU Registers in MFP64 mode. > def D0_64 : AFPR64<0, "F0", [F0]>; > > Notice that we currently need the symbolic name to be different (F0/D0/D0_64) for use in the codegen. > > The examples here are from lib/Target/Mips/MipsRegisterInfo.td. > > Do I just need to use/write another...

On 06/12/2015 07:12 PM, Daniel Sanders wrote: > > Hi, > > I'm afraid targeting a 64-bit CPU and the O32 ABI is completely broken > at the moment, it's one of the very long-standing issues I'm working > towards. The main problem is that a lot of the internals of the Mips > LLVM backend derive their behaviour from the target CPU rather than > the target ABI.

...efficient use of FR=1 mode (FPU >> with 64-bit registers). This is going to be important since MIPS32r6/MIPS64r6 >> will not have direct support for FR=0 mode (FPU with 32-bit registers). At >> the moment, this extension is available in all the tools and is enabled with - >> mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code >> since they require the FPU to be in different modes. To fix the compatibility >> flaw, we are adding an O32 extension called fpxx (enabled with -mfpxx) >> which operates correctly in both FPU modes and is es...

On Wed, Jun 18, 2014 at 2:03 AM, Matheus Almeida <Matheus.Almeida at imgtec.com> wrote: >> Why Imagination Technologies do not offer the latest MIPS ABI document download link just like the ISA docs? > It's something we're considering to do and the documents should be available at some point in the [hopefully] not too distant future. > >> then why GCC disagree with

...nsupported extension that allows the efficient use of FR=1 mode (FPU with 64-bit registers). This is going to be important since MIPS32r6/MIPS64r6 will not have direct support for FR=0 mode (FPU with 32-bit registers). At the moment, this extension is available in all the tools and is enabled with -mfp64. Unfortunately, it is not possible to inter-link O32 and O32+fp64 code since they require the FPU to be in different modes. To fix the compatibility flaw, we are adding an O32 extension called fpxx (enabled with -mfpxx) which operates correctly in both FPU modes and is essentially O32 with some min...

> > I assume with target you mean the backend? Consider the x86 backend. It > supports 32bit and 64bit mode, with the GNU x32 ABI in between. There > are three different executable formats support (ELF, PE, MachO) with > different constraints. Some platforms require 32bit alignment of the > stack, others require 128bit alignment. The list goes on. The triple > specifies >