search for: mfcr

On PowerPC (at least versions which predate the mfocrf instruction), while there are multiple independent condition registers, the only way to move those registers into a general-purpose register is to use mfcr, which transfers all of the (concatenated) condition registers into one general purpose register, followed by a mask/shift operation to extract the desired pieces. I would like to know if there is any way to model this which is compatible with using anti-dependency breaking on the associated condi...

On Jun 9, 2012, at 10:12 PM, Hal Finkel wrote: > On PowerPC (at least versions which predate the mfocrf instruction), > while there are multiple independent condition registers, the only way > to move those registers into a general-purpose register is to use mfcr, > which transfers all of the (concatenated) condition registers into one > general purpose register, followed by a mask/shift operation to extract > the desired pieces. > > I would like to know if there is any way to model this which is > compatible with using anti-dependency br...

Hello! I'm tryuing to bring up an R2 connection but eventhough I've followed the guidelines in: http://zarzamora.com.mx/asterisk/17 something seems to be missing. When an incomming call is generated I get: Nov 24 06:01:17 WARNING[-197416016]: chan_unicall.c:612 unicall_report: MFC/R2 UniCall/24 <- 0001 [1/ 1/Idle /Idle ] Nov 24 06:01:17 WARNING[-197416016]:

...On Jun 9, 2012, at 10:12 PM, Hal Finkel wrote: > > > On PowerPC (at least versions which predate the mfocrf instruction), > > while there are multiple independent condition registers, the only > > way to move those registers into a general-purpose register is to > > use mfcr, which transfers all of the (concatenated) condition > > registers into one general purpose register, followed by a > > mask/shift operation to extract the desired pieces. > > > > I would like to know if there is any way to model this which is > > compatible with usin...

....S --- klibc-0.173/klibc/arch/ppc64/setjmp.S 2003-12-13 14:09:13.000000000 +1030 +++ klibc/klibc/arch/ppc64/setjmp.S 2004-09-15 12:28:42.160328339 +0930 @@ -17,13 +16,33 @@ setjmp: .globl setjmp .globl .setjmp .setjmp: - mflr %r11 /* save return address */ - mfcr %r12 /* save condition register */ - mr %r10,%r1 /* save stack pointer */ - mr %r9,%r2 /* save GPR2 (not needed) */ - stmw %r9,0(%r3) /* save r9..r31 */ - li %r3,0 /* in...

...cho"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; - case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::MFCR: return "PPCISD::MFCR"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMPo: return "PPCISD::VCMPo"; - case PPCISD::LBRX: return "PPCISD::LBRX"; - case PPCISD::STBRX: return "PPCISD::STBRX"...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...cho"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; - case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::MFCR: return "PPCISD::MFCR"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMPo: return "PPCISD::VCMPo"; - case PPCISD::LBRX: return "PPCISD::LBRX"; - case PPCISD::STBRX: return "PPCISD::STBRX"...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...cho"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; - case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::MFCR: return "PPCISD::MFCR"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMPo: return "PPCISD::VCMPo"; - case PPCISD::LBRX: return "PPCISD::LBRX"; - case PPCISD::STBRX: return "PPCISD::STBRX"...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...cho"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho"; - case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::MFCR: return "PPCISD::MFCR"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMPo: return "PPCISD::VCMPo"; - case PPCISD::LBRX: return "PPCISD::LBRX"; - case PPCISD::STBRX: return "PPCISD::STBRX"...

...(arg6); \ + __sc_0 = __NR_##name; \ + __asm__ __volatile__ \ + ("sc \n\t" \ + "mfcr %1 " \ + : "+r" (__sc_3), \ + "+r" (__sc_0), \ + "+r" (__sc_4), \ + "+r" (__sc_5),...

...(arg6); \ + __sc_0 = __NR_##name; \ + __asm__ __volatile__ \ + ("sc \n\t" \ + "mfcr %1 " \ + : "=&r" (__sc_3), "=&r" (__sc_0) \ + : "0" (__sc_3), "1" (__sc_0), \ + "r" (__sc_4),...

...file in NetBSD +# + + .text + .align 4 + + .section ".opd","aw" +setjmp: + .quad .setjmp,.TOC.@tocbase,0 + .previous + .size setjmp,24 + .type .setjmp,@function + .globl setjmp + .globl .setjmp +.setjmp: + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + mr %r10,%r1 /* save stack pointer */ + mr %r9,%r2 /* save GPR2 (not needed) */ + stmw %r9,0(%r3) /* save r9..r31 */ + li %r3,0 /* in...

...jmp: +#else .section ".opd","aw" + .balign 8 setjmp: - .quad .setjmp,.TOC. at tocbase,0 + .quad .setjmp, .TOC. at tocbase, 0 .previous - .size setjmp,24 .type .setjmp, at function - .globl setjmp .globl .setjmp .setjmp: +#endif mflr %r11 /* save return address */ mfcr %r12 /* save condition register */ std %r2,0(%r3) /* save TOC pointer (not needed) */ @@ -43,17 +47,28 @@ setjmp: std %r31,8(%r3) li %r3,0 /* indicate success */ blr /* return */ +#if _CALL_ELF == 2 + .size setjmp,.-setjmp +#else + .size setjmp,.-.setjmp +#endif - .size .setjmp,.-...