search for: mcsym

...for llvm.eh.return() but this will not compile. viz unwind-dw2.c will report: BB#0: derived from LLVM BB %entry Live Ins: %R0 %R0 %R1 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %LR %R0 %R1 ENTSP_lu6 120, %SP<imp-def>, %SP<imp-use>, %LR<imp-use,kill> PROLOG_LABEL <MCSym=.Ltmp68> PROLOG_LABEL <MCSym=.Ltmp69> STWSP_lru6 %R0<kill>, 119, %SP<imp-use> PROLOG_LABEL <MCSym=.Ltmp59> STWSP_lru6 %R1<kill>, 118, %SP<imp-use> PROLOG_LABEL <MCSym=.Ltmp60> STWSP_lru6 %R4<kill>, 11...

...ion::InternalLinkage, "" ... Here is the log of machine instructions before and after emitEpilogue for this function: * PEI::insertPrologEpilogCode: === >> before emitEpilogue - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> - insn: PROLOG_LABEL <MCSym=.Ltmp2> - insn: %RBP<def> = MOV64rr %RSP - insn: PROLOG_LABEL <MCSym=.Ltmp3> - insn: %RDI<def> = MOV64ri64i32 60910096 - insn: %RAX<def> = MOV64ri <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> - insn: TCRETURNri64 %RAX<kill>, 0, %RDI<kill&g...

On Aug 26, 2010, at 12:59 PMPDT, Eric Christopher wrote: > On Aug 26, 2010, at 12:25 PM, Yuri wrote: >> On 08/26/2010 11:53, Eric Christopher wrote: >>> Could you get it to print out the instruction when it happens? >>> (just change the line above the error message to print it out to >>> errs()). >>> >>> It basically means that a pseudo

...t;" ... > > Here is the log of machine instructions before and after > emitEpilogue for this function: > * PEI::insertPrologEpilogCode: === >> before emitEpilogue > - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> > - insn: PROLOG_LABEL <MCSym=.Ltmp2> > - insn: %RBP<def> = MOV64rr %RSP > - insn: PROLOG_LABEL <MCSym=.Ltmp3> > - insn: %RDI<def> = MOV64ri64i32 60910096 > - insn: %RAX<def> = MOV64ri > <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> > - insn: TCRETURNri64 %RAX<kill&g...

...>> >> Here is the log of machine instructions before and after emitEpilogue for this function: >> * PEI::insertPrologEpilogCode: === >> before emitEpilogue >> - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> >> - insn: PROLOG_LABEL <MCSym=.Ltmp2> >> - insn: %RBP<def> = MOV64rr %RSP >> - insn: PROLOG_LABEL <MCSym=.Ltmp3> >> - insn: %RDI<def> = MOV64ri64i32 60910096 >> - insn: %RAX<def> = MOV64ri <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> >> - insn: TCRETURNri64 %RAX&l...

...ains with: *** Bad machine code: MBB exits via unconditional branch but doesn't have exactly one CFG successor! *** - function: t4 - basic block: BB#5 invoke.cont41 The freshly selected relevant blocks are: BB#7: derived from LLVM BB %invoke.cont41 EH_LABEL <MCSym=Ltmp4> B <BB#8> Successors according to CFG: BB#8(1) BB#9(1) BB#8: derived from LLVM BB %invoke.cont43 Predecessors according to CFG: BB#7 BB#9: derived from LLVM BB %lpad40, EH LANDING PAD Predecessors according to CFG: BB#7 EH_LAB...

...= LD %SP, 44; mem:LD4[FixedStack0] (LR is the Return address register) the whole code of print-machineinstrs are: # After PrologEpilogCodeInserter: # Machine code for function L_mpy_ls: Post SSA BB#0: derived from LLVM BB %0 Live Ins: %LR %S1 %S0 %SP<def> = ADDI %SP, -48 PROLOG_LABEL <MCSym=_tmp0> ST %LR<kill>, %SP, 44; mem:ST4[FixedStack0] ST %S1<kill>, %SP, 40; mem:ST4[FixedStack1] ST %S0<kill>, %SP, 36; mem:ST4[FixedStack2] PROLOG_LABEL <MCSym=_tmp1> %S0<def> = LD %SP, 48; mem:LD4[FixedStack-1](align=8) ST %S0, %SP, 0; mem:ST4[FixedStack-4](align=8)...

...tToHPoint: Frame Objects: fi#-1: size=48, align=8, fixed, at location [SP+8] fi#0: size=32, align=8, at location [SP-32] Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 BB#0: derived from LLVM BB %entry Live Ins: %A0 %A2 %A3 %SP<def> = ADDiu %SP, -32 PROLOG_LABEL <MCSym=$tmp0> SW %A3<kill>, %SP, 44; mem:ST4[FixedStack-1+4] SW %A2<kill>, %SP, 40; mem:ST4[FixedStack-1](align=8) %D0<def> = LDC1 %SP, 40; mem:LD8[%x2] The frame index operands of the first two stores and the fourth load have been lowered to real addresses. Since the first two S...

...ost SSA Frame Objects: fi#0: size=1024, align=4, at location [SP-1024] fi#1: size=1024, align=4, at location [SP-2048] BB#0: derived from LLVM BB %entry %ESP<def,tied1> = SUB32ri %ESP<tied0>, 2060, %EFLAGS<imp-def,dead>; flags: FrameSetup PROLOG_LABEL <MCSym=.Ltmp0> CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> %ESP<def,tied1> = ADD32ri %ESP<tied0>, 2060, %EFLAGS<imp-def,dead> RET # End machine code for function main. Let's see what happens if we remove the...

...: > fi#0: size=1024, align=4, at location [SP-1024] > fi#1: size=1024, align=4, at location [SP-2048] > > BB#0: derived from LLVM BB %entry > %ESP<def,tied1> = SUB32ri %ESP<tied0>, 2060, %EFLAGS<imp-def,dead>; flags: FrameSetup > PROLOG_LABEL <MCSym=.Ltmp0> > CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> > %ESP<def,tied1> = ADD32ri %ESP<tied0>, 2060, %EFLAGS<imp-def,dead> > RET > > # End machine code for function main. > > > > Let&...

...gn=4, at location [SP-1024] >> fi#1: size=1024, align=4, at location [SP-2048] >> >> BB#0: derived from LLVM BB %entry >> %ESP<def,tied1> = SUB32ri %ESP<tied0>, 2060, >> %EFLAGS<imp-def,dead>; flags: FrameSetup >> PROLOG_LABEL <MCSym=.Ltmp0> >> CALLpcrel32 <ga:@bar>, <regmask>, %ESP<imp-use>, %ESP<imp-def> >> %ESP<def,tied1> = ADD32ri %ESP<tied0>, 2060, %EFLAGS<imp-def,dead> >> RET >> >> # End machine code for function main. >>...

...: size=48, align=8, fixed, at location [SP+8] > fi#0: size=32, align=8, at location [SP-32] > Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 > > BB#0: derived from LLVM BB %entry > Live Ins: %A0 %A2 %A3 > %SP<def> = ADDiu %SP, -32 > PROLOG_LABEL <MCSym=$tmp0> > SW %A3<kill>, %SP, 44; mem:ST4[FixedStack-1+4] > SW %A2<kill>, %SP, 40; mem:ST4[FixedStack-1](align=8) > %D0<def> = LDC1 %SP, 40; mem:LD8[%x2] > > > The frame index operands of the first two stores and the fourth load > have been lowered to re...

...n [SP+8] >>  fi#0: size=32, align=8, at location [SP-32] >> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 >> >> BB#0: derived from LLVM BB %entry >>    Live Ins: %A0 %A2 %A3 >>       %SP<def> = ADDiu %SP, -32 >>       PROLOG_LABEL <MCSym=$tmp0> >>       SW %A3<kill>, %SP, 44; mem:ST4[FixedStack-1+4] >>       SW %A2<kill>, %SP, 40; mem:ST4[FixedStack-1](align=8) >>       %D0<def> = LDC1 %SP, 40; mem:LD8[%x2] >> >> >> The frame index operands of the first two stores and the fou...

CallFrameSetupOpcode is a pseudo opcode like X86::ADJCALLSTACKDOWN64. That means when the code is expected to be called before the pseudo instructions are eliminated. I don't know why it's not the case for you. A quick look at PEI code indicates the pseudo's should not have been removed at the time when replaceFrameIndices are run. Evan On Sep 25, 2013, at 8:57 AM, Krzysztof

...the log of machine instructions before and after >>> emitEpilogue for this function: >>> * PEI::insertPrologEpilogCode: === >> before emitEpilogue >>> - insn: PUSH64r %RBP<kill>, %RSP<imp-def>, %RSP<imp-use> >>> - insn: PROLOG_LABEL <MCSym=.Ltmp2> >>> - insn: %RBP<def> = MOV64rr %RSP >>> - insn: PROLOG_LABEL <MCSym=.Ltmp3> >>> - insn: %RDI<def> = MOV64ri64i32 60910096 >>> - insn: %RAX<def> = MOV64ri >>> <ga:@_ZN010HelloWorld4mainEPN13ContainerSVecE> >&...

...size=32, align=8, at location [SP-32] >>> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 >>> >>> BB#0: derived from LLVM BB %entry >>> Live Ins: %A0 %A2 %A3 >>> %SP<def> = ADDiu %SP, -32 >>> PROLOG_LABEL <MCSym=$tmp0> >>> SW %A3<kill>, %SP, 44; mem:ST4[FixedStack-1+4] >>> SW %A2<kill>, %SP, 40; mem:ST4[FixedStack-1](align=8) >>> %D0<def> = LDC1 %SP, 40; mem:LD8[%x2] >>> >>> >>> The frame index operands of the fi...

Hi, I've been trying to teach LLVM that pointers are 128-bit long, which segfaults with some seemingly unrelated stacktrace when I try to take an address of a variable. Since stack saving and loading seems to work fine, I dare to assume the instruction causing problems there is leaq. Now I've done a search for leaq of the entire LLVM codebase with no success and I'd like to know which

Hi All, I'm dealing with a problem where the spill/restore instructions inserted during scavenging span an adjustment of the SP/FP register. The result is that despite the base register (SP/FP) being changed between the spill and the restore, both store and load use the same immediate offset. I see code in the PEI (replaceFrameIndices) that is supposed to track the SP/FP adjustment:

...' Aborted" . Could you please help resolve the problem. I guess I may be doing the wrong thing somewhere. The assembly code generated for the function is: BB#0: derived from LLVM BB %entry %RSP<def> = SUB64ri8 %RSP, 24, %EFLAGS<imp-def,dead>; dbg:l8.cpp:1:1 PROLOG_LABEL <MCSym=.Ltmp0>; dbg:l8.cpp:1:1 DBG_VALUE %EDI, 0, !"arg1"; dbg:l8.cpp:3:1 MOV32mi %RSP, 1, %reg0, 20, %reg0, 21; mem:ST4[%X] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 16, %reg0, 22; mem:ST4[%Y] dbg:l8.cpp:1:1 MOV32mi %RSP, 1, %reg0, 12, %reg0, 23; mem:ST4[%Z] dbg:l8.cpp:1:1 %EDI<def> = MOV...

...cation [SP-32] >>>> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 >>>> >>>> BB#0: derived from LLVM BB %entry >>>>    Live Ins: %A0 %A2 %A3 >>>>       %SP<def> = ADDiu %SP, -32 >>>>       PROLOG_LABEL <MCSym=$tmp0> >>>>       SW %A3<kill>, %SP, 44; mem:ST4[FixedStack-1+4] >>>>       SW %A2<kill>, %SP, 40; mem:ST4[FixedStack-1](align=8) >>>>       %D0<def> = LDC1 %SP, 40; mem:LD8[%x2] >>>> >>>> >>>> The frame in...