Displaying 2 results from an estimated 2 matches for "mcoreinstrinfo".
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2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In...
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
...;
}
// Load/Store Multiple Register Mode
class MultR<bits<2> subOpVal, dag outs, dag ins, string asmstr,
list<dag> pattern> : MABase<outs, ins, asmstr, pattern> {
let subOp = subOpVal;
}
Finally, I don't know how to describe following instructions in
MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
should I use to finish this description?
// LDQ, STQ, LDM and STM are Mapping Error
// Load/Store Register Quadrant Mode
def LDQ : QuadR<0x0, // FIXME p81
(outs GPRs:$Rx), (ins GPRs:R4, GPRs:R5, GPRs:R6, GPRs:R7),...