search for: xcoreinstrinfo

...g a global address to a target global address XCoreISelLowering wraps the tglobaladdress node with one of three wrappers (PCRelativeWrapper, DPRelativeWrapper, CPRelativeWrapper) based on properties of the global (is it a function, is it constant, etc) . > > The wrapper is used in patterns in XCoreInstrInfo.td to ensure the right instruction is selected to access the global (for example to get the address of the global into a register the backend uses the LDAP instruction if the PCRelativeWrapper is present, LDAWCP if the CPRelativeWrapper is present and LDAWDP if the DPRelativeWrapper is present). &g...

...n lowering a global address to a target global address XCoreISelLowering wraps the tglobaladdress node with one of three wrappers (PCRelativeWrapper, DPRelativeWrapper, CPRelativeWrapper) based on properties of the global (is it a function, is it constant, etc) . The wrapper is used in patterns in XCoreInstrInfo.td to ensure the right instruction is selected to access the global (for example to get the address of the global into a register the backend uses the LDAP instruction if the PCRelativeWrapper is present, LDAWCP if the CPRelativeWrapper is present and LDAWDP if the DPRelativeWrapper is present).

...t modifying llvm? > > Regards, Christian The XCore has loads / stores where the offset is scaled by the size of the load or store. For example the load word instruction LDW takes an offset which is multiplied by 4 and added to the base pointer. This is dealt with in the patterns defined in XCoreInstrInfo.td. The following pattern is used for LDW: def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; immUs4 is true when offset is a multiple of 4 and the offset divided by 4 fits in an immediate. The div4_xform xform divides a c...

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to

Hi, my target architecture has a kind of "16bit addressing mode", i.e. one address does not address 8 bit but a 16bit chunk. Consequently, every constant used to calculate effective addresses must be divided by two. So far this is not such a problem for stack objects since FrameIndexes, function arguments etc. have a lot of custom lowering code where this can be done. But when it comes

On 25/07/12 12:14, Paul Shortis wrote: > Thanks Richard, > > You're correct, they are similar. In the XCoreInstrInfo.td patterns > what I'm struggling with is why this .... > > def BL_lu10 : _FLU10< > (outs), > (ins calltarget:$target, variable_ops), > "bl $target", > [(XCoreBranchLink immU20:$target)]&g...

I am using LLVM 2.8 on Ubuntu 10.10. (new to both) I change name of instruction on XXXInstrInfo.td ( Sparc, X86 and XCore). I looked into XXXGenAsmWriter.inc and I have seen the new instruction name. But when I run llc for the three targets it prints out the old instruction name. For example for XCore I change “divs” to “sdiv” like >From => def DIVS_l3r :

On 13 January 2011 19:20, Atse Zeriakob <atsezeriakob at gmail.com> wrote: > For example in XCoreInstrInfo.td I change the name of one of the instruction > let say "divs" to "newdivs", > > like > def DIVS_l3r : FL3R<"newdivs", sdiv>; > > When I run llc with option -march=xcore, after I make the modification, it > still outputs "divs", no...

...m using LLVM 2.8 on Ubuntu 10.10. (new to both) I change name of instruction on XXXInstrInfo.td ( Sparc, X86 and XCore). I looked into XXXGenAsmWriter.inc and I have seen the new instruction name. But when I run llc for the three targets it prints out the old instruction name. For example in XCoreInstrInfo.td I change the name of one of the instruction let say "divs" to "newdivs", like def DIVS_l3r : FL3R<"newdivs", sdiv>; When I run llc with option -march=xcore, after I make the modification, it still outputs "divs", not "newdivs". I loo...

Have you added the $LLVM_INSTALL_DIR/bin to your PATH environment variable? Regarding changing a particular backend, check the documentation in http://llvm.org/docs/WritingAnLLVMBackend.html http://llvm.org/docs/CodeGenerator.html A few LLVMdev meetings have good talks to give you a good enough idea. http://llvm.org/devmtg/ Cheers, Raghu. ----- Original Message ----- From: "Teklu

...> > Regards, Christian > The XCore has loads / stores where the offset is scaled by the size of > the load or store. For example the load word instruction LDW takes an > offset which is multiplied by 4 and added to the base pointer. This is > dealt with in the patterns defined in XCoreInstrInfo.td. The following > pattern is used for LDW: > > def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), > (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; > Richard, thanks for your suggestion. However, I think what you describe is what I meant by 'only catc...

Hi I am new to llvm and Linux (I am using ubuntu 10) My aim is to add backend to llvm. I install llvm using $ sudo apt-get install llvm and I am able to understand what I read about Writing an LLVM Compiler Backend. I have seen the assembly codes of the targets on llvm using llc. What I need now is to change some of the TableGen files of one of the target like SparcInstrInfo.td.  So I