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...m inserter. I added a pass to expand the remaining shift pseudos into shift and rotate sequences with masking where required (e.g. replacing SRL x,7 with ROL x,2) > > I've no idea if that's the best way but it seems to work for me. > > Steve > > On 9 Nov 2013, at 21:29, MathOnNapkins . <mathonnapkins at gmail.com> wrote: > >> Dear All, >> >> I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "...

...ngly (to me) equivalent lines of code cause different behavior at run time. For reference, each of my pseudo instructions expands to 2 or more native instructions. p_mi->removeFromParent() seems to be used in other targets ( but not expandPostRAPseudo() ) without issue.... *shrug*. Sincerely, ~ MathOnNapkins / David On Mon, Jan 14, 2013 at 4:14 AM, Duncan Sands <baldrick at free.fr> wrote: > Hi David, > > > > Previously, I had been testing with only one routine per test .ll file, > but I > >> thought I'd reached a point where I could test multiple operations at &...

..., is the MSP430, and it's still a bit experimental (though a very helpful example for me at times). Could I also ask whether you had to design your shift nodes with Glue or Chain operands? I haven't taken extra that step yet, but I imagine it will be necessary. Sincerely, ~Dave Waggoner / MathOnNapkins On Sun, Nov 10, 2013 at 1:35 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the > high and low parts of an SDValue. > > On 10 Nov 2013, at 17:50, Steve Montgomery < > stephen.mont...

removeFromParent just unlinks it from the basic block and returns the removed instruction. It does not delete it. On Sun, Jan 20, 2013 at 9:54 PM, David Waggoner <mathonnapkins at gmail.com>wrote: > > Thanks for the suggestion, Duncan. > > I recently figured out that it had to do with how I was removing the > pseudo instruction in my overridden expandPostRAPseudo() implementation. > > // member function's signature > bool TheInstrInfo::expa...

...mple: asl %b rol %c asl %b rol %c There doesn't seem to be a set of standard node types analogous to ADD / ADDC / ADDE for shift operations, which is really what I'm after here. I would very much appreciate any advice or insight you could provide on this matter. Thanks, ~Dave Waggoner / MathOnNapkins -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131109/c5b92890/attachment.html>

...using a loop so I used a custom inserter. I added a pass to expand the remaining shift pseudos into shift and rotate sequences with masking where required (e.g. replacing SRL x,7 with ROL x,2) I've no idea if that's the best way but it seems to work for me. Steve On 9 Nov 2013, at 21:29, MathOnNapkins . <mathonnapkins at gmail.com> wrote: > Dear All, > > I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or &q...

...2 22 llc 0x08c46528 llvm::PassManagerImpl::run(llvm::Module&) + 168 23 llc 0x08c46636 llvm::PassManager::run(llvm::Module&) + 38 24 llc 0x0818513a main + 4026 25 libc.so.6 0xb74546b3 __libc_start_main + 243 26 llc 0x08195e8d Stack dump: 0. Program arguments: /home/MathOnNapkins/Documents/Programming/llvm-3.2/Release+Asserts/bin/llc -march=x65 -debug -filetype=asm ./test.ll 1. Running pass 'Function Pass Manager' on module './test.ll'. 2. Running pass 'x65 DAG->DAG Pattern Instruction Selection' on function '@foo_and32' For referen...

...achineFunction() in my XXXISelDagToDag.cpp > file, so this is happening somewhat out of my control. Should I attempt to > override it? I noticed that only a couple targets actually override > runOnMachineFunction() for that particular pass (MIPS, I think is one). > > Sincerely, > ~MathOnNapkins / Dave > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >

...his problem. Should I create a new pass to run after Post Regalloc to correct my Machine Functions? That seems like a last ditch effort at fixing the problem though, and I'd rather resolve it through some other means if possible. Any input would be much appreciated. Thank You, ~Dave Waggoner / MathOnNapkins -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131124/73bce9ed/attachment.html>

Dear All, I think I understand the motivation for these node types, but I'm not positive: " /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded /// integer shift operations, just like ADD/SUB_PARTS. The operation /// ordering is: /// [Lo,Hi] = op [LoLHS,HiLHS], Amt SHL_PARTS, SRA_PARTS, SRL_PARTS " Okay, for one thing, I can't