search for: matchinstructionimpl

...nsigned Opcode, const SmallVectorImpl<MCParsedAsmOperand*> &Operands); void convertToMapAndConstraints(unsigned Kind, const SmallVectorImpl<MCParsedAsmOperand*> &Operands); bool mnemonicIsValid(StringRef Mnemonic); unsigned MatchInstructionImpl( const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst, unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID = 0); enum OperandMatc...

...const SmallVectorImpl<MCParsedAsmOperand*> &Operands); > void convertToMapAndConstraints(unsigned Kind, > const > SmallVectorImpl<MCParsedAsmOperand*> &Operands); > bool mnemonicIsValid(StringRef Mnemonic); > unsigned MatchInstructionImpl( > const > SmallVectorImpl<MCParsedAsmOperand*> &Operands, > MCInst &Inst, > unsigned &ErrorInfo, bool matchingInlineAsm, > unsigned VariantID...

Dear all, I have written an assembler which reads assembly instructions and produces the equivalent binary. I have a problem. Although I set the bit range and immediate type for an instruction like add which accepts a register and an immediate value, I can simply overflow that value and llvm/tablegen doesn't care! for example for a i8imm imm value (bits<8> val) these two produce the

...Feature_IsFP64bit, 0}, { Mips::CEIL_W_D32, 93 /* ceil */, Convert__Reg1_2__Reg1_3, { MCK__DOT_w, MCK__DOT_d, MCK_FGR32, MCK_AFGR64 }, Feature_NotFP64bit, 0}, { Mips::CEIL_W_S, 93 /* ceil */, Convert__Reg1_2__Reg1_3, { MCK__DOT_w, MCK__DOT_s, MCK_FGR32, MCK_FGR32 }, 0, 0}, . . . } So, when the MatchInstructionImpl is called it seems to look for a pair of instructions that match the mnemonic: // Search the table. std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange = std::equal_range(MatchTable, MatchTable+277, Mnemonic, LessOpcode()); The search will always end in first two entries (...

...x Rx ." format that is expected by the assembly parsing infrastructure, represented by: StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); This Mnemonic location assumption applies to both the Tablegen Backend AsmMatcherEmitter processing, and the .inc file it produces where MatchInstructionImpl is the entry point by which the assembly input is parsed. However Hexagon assembly has some features that make it more readable, such as r1 = r2, or if(r1) r2 = mem(#immediate). This makes taking advantage of the existing LLVM code difficult. Currently, I see two options. One is...

...ts so that the base mnemonic and the suffices are distinct for the matcher. ARM does similar things. I suggest looking there an example of how this might be done. Avert your eyes from some of the other horrible hackery in that function, though. ;) -Jim > . > . > } > > So, when the MatchInstructionImpl is called it seems to look for a pair of instructions that match the mnemonic: > > // Search the table. > std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange = > std::equal_range(MatchTable, MatchTable+277, Mnemonic, LessOpcode()); > > The search will alwa...

...format that is expected by the assembly parsing infrastructure, represented by: > StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); > > This Mnemonic location assumption applies to both the Tablegen Backend AsmMatcherEmitter processing, and the .inc file it produces where MatchInstructionImpl is the entry point by which the assembly input is parsed. > > However Hexagon assembly has some features that make it more readable, such as r1 = r2, or if(r1) r2 = mem(#immediate). This makes taking advantage of the existing LLVM code difficult. > > > Currently, I see two opt...

...simple AsmParser for my backend. llvm-tablegen also generates asm-matcher .inc file without any error. I have included the .inc file in my class for AsmParser. However, while building llvm, in linking stage for LTO, i am getting error - undefined reference to functions - ComputeAvailableFeatures, MatchInstructionImpl, MatchRegisterName and convertToMapAndConstraints. I see these functions declared and defined in GenAsmMatcher.inc file which i have included in my AsmParser class. Still i am getting the error. I may be missing something very basic. Can someone please help in resolving this error? Thanks. Reg...

I'm trying to add support for inline assembly and I keep getting this error: <jal> "<inline asm>:1:2: error: invalid instruction" which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0[] and MnemonicTable The input was int main () { asm volatile ("JAL"); return 0; } If I go to JAL's d...

...^ rather than: /tmp/foo.s:1:2: error: instruction requires: distinct-ops sllk %r2,%r3,1 ^ This is because MatchOperandParserImpl() skips custom parsers if the subtarget feature isn't enabled, so the instruction is parsed using the default operand parser instead. Then MatchInstructionImpl() only returns Match_MissingFeature if an otherwise good match is found, which in my case requires the custom parser to be used. ARM seems to rely on the current MatchOperandParserImpl() behaviour, so I'm not going to suggest changing it unconditionally. But on SystemZ there aren't any ca...

...egister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); @@ -53,37 +46,106 @@ private: /// @name Auto-generated Match Functions /// { - bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands, - MCInst &Inst); - bool MatchInstructionImpl( const SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCInst &Inst); /// } public: - X86ATTAsmParser(const Target &T, MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) {} + X86ATTAsmParser(const Target &T, bool _Is64Bit, AsmParser *_Parser) {...