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2013 May 16
0
[LLVMdev] Combining physical registers
...0, then SubA is completely covered by
> /// SubB.
> unsigned getCoveringLanes() const { return CoveringLanes; }
Yes, this would solve my problem. I'm assuming that if I have
subregisters Sub0..SubN (where Sub0 could be 0, i.e. the register
itself), and corresponding masks Mask0..MaskN, and
Mask0 & ~((Mask1|Mask2|..|MaskN) & Covering) == 0,
this will imply that the subregisters Sub1..SubN cover Sub0.
Thanks,
-Krzysztof
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2013 May 16
1
[LLVMdev] Combining physical registers
On May 16, 2013, at 8:13 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote:
> The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores