search for: masked_gather

...i64 = BUILD_VECTOR Constant:i64<31>, Constant:i64<31>, Constant:i64<31>, Constant:i64<31> Once I have defined type v128i64 in the above mentioned 4 files (2 .td, 1 .h, 1 .cpp), I no longer get this strange error. However, now I start getting Segfault at selection for masked_gather, the reason being that I don't have vector registers of 64-bits: ISEL: Starting pattern match on root node: t14: v128i16,ch = masked_gather<LD256[<unknown>]> t0, t22, t29, TargetConstant:i64<0>, t33 Initial Opcode index to 1692 #0 0x00007f08faa9e700 llvm...

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile - This profile describes the type requirements of a Selection...

...;getNumTypes() == 1 && "FIXME: Unhandled"' failed." Can somebody help me with the code below responsible for this error? // From llvm/lib/Target/X86/X86InstrFragmentsSIMD.td def mgatherv128i16 : PatFrag<(ops node:$src1, node:$src2, node:$src3), (masked_gather node:$src1, node:$src2, node:$src3) , [{ if (MaskedGatherSDNode *mgNode = dyn_cast<MaskedGatherSDNode>(N)) return (mgNode->getIndex().getValueType() == MVT::v128i16 || mgNode->getBasePtr().getValueType() == MVT::v128i16); return false; }]>...

...lows: def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst, VK64WM:$mask_wb), (ins VR_2048:$src1, VK64WM:$mask, i2048mem:$src2), "GATHER_256B\t{$src2, {$dst} {${mask}}|${dst} {${mask}}, $src2}", [(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32 (masked_gather (VR_2048:$src1), VK64WM:$mask, addr:$src2)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather (VR_2048:$src1), (VK64WM:$mask),(addr:$src2))), (GATHER_256B VR_2048:$src1, VK64WM:$mask, addr:$src2)>; Now getting this error: llvm-tblgen: /utils...

...rking backwards from here, the actual PatFrags passed into this are things like ‘mgatherv4i32’. These are patterns that match a MaskedGatherSDNode for a particular data type. MaskedGatherSDNode is the generic SD node that represents a predicated gather, which in turn was generated from Intrinsic::masked_gather in the IR (in SelectionDAGBuilder::visitMaskedGather) If your MIPS instruction has a predicate, you will need to create MIPS tablegen that matches MaskedGatherSDNode. If not, I guess you’ll need to create a new intrinsic that represents an unpredicted gather, and add appropriate uses of it during...

...; i < 800; i++) { A[B[i]] = i + 5; } for (int i = 0; i < 800; i++) { A[B[i]]++; } for (int i = 0; i < 800; i++) { A[i] = B[C[i]]; } return 0; } Could some give me an example that will generate gather intrinsic for AVX2? I tried to used the masked_gather intrinsic provided in the language ref. But it seemed that it only generates gather intrinsic for AVX-512 but for AVX-2. I found that there are 16 gather intrinsic versions depending on the data types provided for AVX-2. Do I have to check the data type before calling them specifically? or is there...

...erNode (VR_2048:$src1), _.KRCWM:$mask, VR_2048:$src2))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (GatherNode addr:$src2)), (GATHER_256B addr:$src2)>; Thank You On Mon, Aug 7, 2017 at 2:57 AM, Craig Topper <craig.topper at gmail.com> wrote: > masked_gather returns two results. The data and the modified mask. Note > the $dst and the $mask_wb in the pattern below. > > multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _, > X86MemOperand memop, PatFrag GatherNode> { > let Constra...

Hello. I read on page 4 of http://www.cs.fsu.edu/~whalley/cda5155/chap4.pdf that gather and scatter operations exist for Mips, named LVI and SVI, respectively. Did anyone think of implementing in the LLVM Mips back end (part of the MSA vector instructions) gather and scatter operations? If so, can you share with me the TableGen spec? (I tried to start from LD_DESC_BASE, but it

...gt; A[B[i]]++; >> } >> >> for (int i = 0; i < 800; i++) { >> A[i] = B[C[i]]; >> } >> return 0; >> } >> >> Could some give me an example that will generate gather intrinsic for >> AVX2? I tried to used the masked_gather intrinsic provided in the language >> ref. But it seemed that it only generates gather intrinsic for AVX-512 but >> for AVX-2. I found that there are 16 gather intrinsic versions depending on >> the data types provided for AVX-2. Do I have to check the data type before >> ca...

i want to implement gather for v64i32. i wrote following code. def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins i2048mem:$src), "GATHER_256B\t{$src, $dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>; Also i wrote this line in isellowering.h setOperationAction(ISD::MGATHER, MVT::v64i32, Legal); But I am getting following error: llvm-tb...

Hello, my target support maximum gather of v64i32....i want to lower all the greater gathers to v64i32. for this i used; setOperationAction(ISD::MGATHER, MVT::v128i32, Expand); but i am getting error; LLVM ERROR: Cannot select: t4257: v128i32,ch = masked_gather<LD512[<unknown>](align=4)(tbaa=<0x30e7c78>)> t0, undef:v128i32, t4394, TargetConstant:i64<0>, t4312 t1061: v128i32 = undef t4394: v128i1 = BUILD_VECTOR TargetConstant:i1<-1>, TargetConstant:i1<-1>, TargetConstant:i1<-1>, TargetConstant:i1<-1>,.......

...*> %gep.addr, i32 8, <2 x i1> <i1 true, i1, true>, <2 x double> undef) I could load my pass successfully with opt, but I got the following errors when I either run the new bitcode using lli or generate the assembly using llc: PromoteIntegerOperand Op #2: 0x41bf3a8: v2f64,ch = masked_gather 0x415ec40, 0x41bf030, 0x41bf280, 0x41bbb30, 0x41becb8<LD16[%a]> [ORD=8] [ID=0] Do not know how to promote this operator's operand! Any idea about this error? Or could anyone give me an example how to use the gather intrinsic if there is something wrong with the way I am using it? Best,...

...; i < 800; i++) { A[B[i]] = i + 5; } for (int i = 0; i < 800; i++) { A[B[i]]++; } for (int i = 0; i < 800; i++) { A[i] = B[C[i]]; } return 0; } Could some give me an example that will generate gather intrinsic for AVX2? I tried to used the masked_gather intrinsic provided in the language ref. But it seemed that it only generates gather intrinsic for AVX-512 but for AVX-2. I found that there are 16 gather intrinsic versions depending on the data types provided for AVX-2. Do I have to check the data type before calling them specifically? or is there...

Hi, Recent Intel architectures AVX-512 and AVX2 provide vector gather and/or scatter instructions. Gather/scatter instructions allow read/write access to multiple memory addresses. The addresses are specified using a base address and a vector of indices. We'd like Vectorizers to tap this functionality, and propose to do so by introducing new intrinsics: VectorValue = @llvm.sindex.load