search for: mask_base

Hi, Keir, Jan, This patch is a bugfix pointed by Jan. Fix mask_base(actually MSI-X table base, copy name from native) to be a virtual address rather than a physical address. And remove wrong printk in pci_disable_msix. Jan, the error message you saw is wrong output from kernel''s MSI code. Really sorry for my dirty code there. Could you please review the...

...l_find_entry( return NULL; } +static struct msi_desc *virt_to_msi_desc(struct pci_dev *dev, void *virt) +{ + struct msi_desc *desc; + + list_for_each_entry( desc, &dev->msi_list, list ) + if ( desc->msi_attrib.type == PCI_CAP_ID_MSIX && + desc->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET + == virt ) + return desc; + + return NULL; +} + static void __iomem *msixtbl_addr_to_virt( struct msixtbl_entry *entry, unsigned long addr) { @@ -247,13 +260,16 @@ out: } static int msixtbl_write(struct vcpu *v, unsigned...

...; void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) > { > if (entry->dev->current_state != PCI_D0) { > /* Don't touch the hardware now */ > } else if (entry->msi_attrib.is_msix) { > void __iomem *base; > base = entry->mask_base + > entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; > > writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); > writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); > writel(msg->data, base + PCI_MSIX_ENTRY_DATA); >...

...irq(struct msi_desc *desc, u32 flag) +{ + desc->masked = arch_msix_mask_irq(desc, flag); +} + +static void msi_set_mask_bit(struct irq_data *data, u32 flag) +{ + struct msi_desc *desc = irq_data_get_msi(data); + + if (desc->msi_attrib.is_msix) { + msix_mask_irq(desc, flag); + readl(desc->mask_base); /* Flush write to device */ + } else { + unsigned offset = data->irq - desc->irq; + msi_mask_irq(desc, 1 << offset, flag << offset); + } +} + +void mask_msi_irq(struct irq_data *data) +{ + msi_set_mask_bit(data, 1); +} + +void unmask_msi_irq(struct irq_data *data) +{ + msi_se...

...c->masked = arch_msix_mask_irq(desc, flag); > +} > + > +static void msi_set_mask_bit(struct irq_data *data, u32 flag) > +{ > + struct msi_desc *desc = irq_data_get_msi(data); > + > + if (desc->msi_attrib.is_msix) { > + msix_mask_irq(desc, flag); > + readl(desc->mask_base); /* Flush write to device */ > + } else { > + unsigned offset = data->irq - desc->irq; > + msi_mask_irq(desc, 1 << offset, flag << offset); > + } > +} > + > +void mask_msi_irq(struct irq_data *data) > +{ > + msi_set_mask_bit(data, 1); > +} > +...

...c->masked = arch_msix_mask_irq(desc, flag); > +} > + > +static void msi_set_mask_bit(struct irq_data *data, u32 flag) > +{ > + struct msi_desc *desc = irq_data_get_msi(data); > + > + if (desc->msi_attrib.is_msix) { > + msix_mask_irq(desc, flag); > + readl(desc->mask_base); /* Flush write to device */ > + } else { > + unsigned offset = data->irq - desc->irq; > + msi_mask_irq(desc, 1 << offset, flag << offset); > + } > +} > + > +void mask_msi_irq(struct irq_data *data) > +{ > + msi_set_mask_bit(data, 1); > +} > +...

...ntry = NULL; @@ -228,8 +230,19 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq) entry = irq_get_msi_desc(irq); } - if (entry) + if (entry) { write_msi_msg(irq, &entry->msg); + if (dev->msix_enabled) { + msix_mask_irq(entry, entry->masked); + readl(entry->mask_base); + } else { + pos = entry->msi_attrib.pos; + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, + &control); + msi_mask_irq(entry, msi_capable_mask(control), + entry->masked); + } + } } #endif @@ -406,7 +419,6 @@ static void __pci_restore_msi_state(struct pci_dev...

...64BIT) @@ -699,7 +698,6 @@ static int msix_setup_entries(struct pci_dev *dev, void __iomem *base, entry->msi_attrib.is_64 = 1; entry->msi_attrib.entry_nr = entries[i].entry; entry->msi_attrib.default_irq = dev->irq; - entry->msi_attrib.pos = dev->msix_cap; entry->mask_base = base; list_add_tail(&entry->list, &dev->msi_list); diff --git a/include/linux/msi.h b/include/linux/msi.h index 8103f32..ce88c5b 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -29,7 +29,6 @@ struct msi_desc { __u8 multi_cap : 3; /* log2 num of messages suppor...

...; } } void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { - BUG_ON(entry->dev->current_state != PCI_D0); + struct pci_dev *dev = entry->msi->data; + + BUG_ON(dev->current_state != PCI_D0); if (entry->msi_attrib.is_msix) { void __iomem *base = entry->mask_base + @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg) msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); msg->data = readl(base + PCI_MSIX_ENTRY_DATA); } else { - struct pci_dev *dev = entry->dev; int pos = dev->msi_cap; u16 data;...

...truct msi_desc *entry, struct msi_msg *msg) >> { >> if (entry->dev->current_state != PCI_D0) { >> /* Don't touch the hardware now */ >> } else if (entry->msi_attrib.is_msix) { >> void __iomem *base; >> base = entry->mask_base + >> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >> >> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); >> writel(msg->data, base + PCI_MSIX_EN...

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

Hi all, The series is a draft of generic MSI driver that supports PCI and Non-PCI device which have MSI capability. If you're not interested it, sorry for the noise. The series is based on Linux-3.16-rc1. MSI was introduced in PCI Spec 2.2. Currently, kernel MSI driver codes are bonding with PCI device. Because MSI has a lot advantages in design. More and more non-PCI devices want to use

...msi_desc *entry, struct msi_msg *msg) > { > - BUG_ON(entry->dev->current_state != PCI_D0); > + struct pci_dev *dev = entry->msi->data; > + > + BUG_ON(dev->current_state != PCI_D0); > > if (entry->msi_attrib.is_msix) { > void __iomem *base = entry->mask_base + > @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg > *msg) > msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); > msg->data = readl(base + PCI_MSIX_ENTRY_DATA); > } else { > - struct pci_dev *dev = entry->dev; > int p...

...msi_desc *entry, struct msi_msg *msg) > { > - BUG_ON(entry->dev->current_state != PCI_D0); > + struct pci_dev *dev = entry->msi->data; > + > + BUG_ON(dev->current_state != PCI_D0); > > if (entry->msi_attrib.is_msix) { > void __iomem *base = entry->mask_base + > @@ -271,7 +294,6 @@ void __read_msi_msg(struct msi_desc *entry, struct msi_msg > *msg) > msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR); > msg->data = readl(base + PCI_MSIX_ENTRY_DATA); > } else { > - struct pci_dev *dev = entry->dev; > int p...

...truct msi_msg *msg) >>> { >>> if (entry->dev->current_state != PCI_D0) { >>> /* Don't touch the hardware now */ >>> } else if (entry->msi_attrib.is_msix) { >>> void __iomem *base; >>> base = entry->mask_base + >>> entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; >>> >>> writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); >>> writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); >>> writel(msg->data...

...y( return NULL; } +static struct msi_desc *virt_to_msi_desc(struct pci_dev *dev, void *virt) +{ + struct msi_desc *desc; + + list_for_each_entry( desc, &dev->msi_list, list ) + if ( desc->msi_attrib.type == PCI_CAP_ID_MSIX && + virt >= desc->mask_base && + virt < desc->mask_base + PCI_MSIX_ENTRY_SIZE ) + return desc; + + return NULL; +} + static void __iomem *msixtbl_addr_to_virt( struct msixtbl_entry *entry, unsigned long addr) { @@ -247,13 +260,16 @@ out: } static int msixtbl_write(struct vcp...

On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: > Hi Brian, > From your 01:00.0 VGA compatible controller PCI config register, it supports 1 MSI vector, so I think this > card has no problem. But you didn't answer what's the pci_enable_msi() return during it enable MSI fail. > > You can check PCI bus whether support MSI like: > >

...cking code in __write_msi_msi. void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg) { if (entry->dev->current_state != PCI_D0) { /* Don't touch the hardware now */ } else if (entry->msi_attrib.is_msix) { void __iomem *base; base = entry->mask_base + entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE; writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR); writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); ...... > shouldn't. I...