Displaying 16 results from an estimated 16 matches for "mask2".
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2000 Aug 24
2
hosts allow/deny question
Hi all,
I would like to do something like this at Samba level:
hosts allow = subnet1/mask1 subnet2/mask2 etc
hosts deny = *
But this doesn't seem to work (machine that are not in subnet1 and
not in subnet2 still have access)
I think the * is not understood by Samba, I tried ALL, this didn't
work either. I'm gonna check the samba source code but if I could
get an expert answer that'd...
2013 May 16
0
[LLVMdev] Combining physical registers
...by
> /// SubB.
> unsigned getCoveringLanes() const { return CoveringLanes; }
Yes, this would solve my problem. I'm assuming that if I have
subregisters Sub0..SubN (where Sub0 could be 0, i.e. the register
itself), and corresponding masks Mask0..MaskN, and
Mask0 & ~((Mask1|Mask2|..|MaskN) & Covering) == 0,
this will imply that the subregisters Sub1..SubN cover Sub0.
Thanks,
-Krzysztof
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
2006 Jun 24
2
data frame search
Hi,
I want to make a data frame which contains the positions of some searched values in another data frame.
Like:
Dataframe 1:
1 2 3 4 1 2 3 4
2 3 4 1 2 3 4 2
4 1 2 3 2 3 4 1
Let's say I searched on "4", then Dataframe 2 should contain:
x y
1 4
1 8
2 3
2 7
3 1
3 7
I have written a routine, but it seems to me that it isn't that perfect:
x<- 0
2008 Jul 17
2
[LLVMdev] ComputeMaskedBits Bug
...< 3, sh r849 << 6 + SR_S112.0)
ComputeMaskedBits correctly identifies the recurrence and sets
L = %r851 = shl i64 %r849, 6 ; <i64> [#uses=16]
R = %r862 = shl i64 %r849, 3
ComputeMaskedBits on R returns KnownZero as 0x7, as expected.
The PHI-analysis code in ComputeMaskedBits sets Mask2 to 0x7. It then calls
itself recursively on L passing Mask2 as the mask.
Here's where the problem creeps in. ComputeMaskedBits returns KnownZero as
0x3f for L. Shouldn't the passed Mask limit it to returning 0x7 since the
comment at the top of ComputeMaskedBits says:
"This code...
2012 Apr 05
1
[PATCH] remove unnecesary typedef in bitwriter.c
...ts <= FLAC__BITS_PER_WORD) { /* i.e. if the whole thing fits in the current uint32_t */
+ /* ^^^ if bw->bits is 0 then we may have filled the buffer and have no free uint32_t to work in */
bw->bits = bw->bits + msbits + lsbits;
uval |= mask1; /* set stop bit */
uval &= mask2; /* mask off unused top bits */
@@ -557,8 +556,8 @@ FLAC__bool FLAC__bitwriter_write_rice_signed_block(FLAC__BitWriter *bw, const FL
}
else {
#elif 1 /*@@@@@@ OPT: try this version with MSVC6 to see if better, not much difference for gcc-4 */
- if(bw->bits && bw->bits + msbits...
2015 Dec 28
1
[PATCH 3] for bitwriter.c
...Asserts like
FLAC__ASSERT(parameter < sizeof(unsigned)*8)
were changed to
FLAC__ASSERT(parameter < 32)
I don't understand why sizeof is better here. Also, bitreader.c already uses
asserts like "FLAC__ASSERT(parameter <= 31)".
4) Fixed the calculation of mask1 and mask2. The current code is incorrect
if FLAC__WORD_ALL_ONES is not 32-bit, so better to replace it with the
proper 32-bit constant.
5) In FLAC__bitwriter_write_rice_signed_block() the new variable total_bits
was added (just as in FLAC__bitwriter_write_rice_signed()). The code was
simplified. Example:
-...
2005 Oct 18
0
Two differente networks at the same ethernet pci adapter
Hello all,
I need to put an IP alias to the same ethernet card, like this:
eth0 - IP1/MASK1/BROADCAST1
eth0:1 - IP2/MASK2/BROADCAST2
In this box I will have another card that conects to a LAN netowork. I
need this two alias in eth0 becouse I have two routes do take, but it seens
to do not work. This is the script I am using (this scripts works fine when
I have two ethernet cards like eth0 and eth1 for backbone...
2013 May 16
1
[LLVMdev] Combining physical registers
On May 16, 2013, at 8:13 AM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote:
> The function TII::canCombineSubRegIndices has been gone for a while now, and I was wondering if there is a target-independent way of determining if a certain set of physical registers "adds up" to a larger register. For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1 are
2005 Jul 23
3
Multiple ISP Provider on one interface
The problem is that I have only 2 ethernet adapters in my linux router,
one of this adapter pluged to the LAN and the other is pluged to a HUB
who have 2 routers DSL. Each DSL routers have an static ip and the
solution that I found was creating an eth0 and eth0:1 but with this
option I have any way to use the eth0:1 adapte...
Any one knows a solution for this ?
Regards.
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores
2015 Dec 16
2
about word size in bitreader/bitwriter
...ed)(word & 0xff), crc);
}
#else
...
This implies that there was intention to set FLAC__BYTES_PER_WORD to 8 on 64-bit
architectures. However currently the code in bitreader.c/bitwriter.c doesn't care
much about 64-bit words: there are places like
const FLAC__uint32 mask2 = FLAC__WORD_ALL_ONES >> (31-parameter);
and FLAC__bitwriter_write_raw_uint64() simply calls FLAC__bitwriter_write_raw_uint32() twice...
And there were three patches --
<http://git.xiph.org/?p=flac.git;a=commitdiff;h=66bd44bacc28cb154b5c9349cf3288da9ec74501>
<http://git.xiph.org/...
2011 Dec 02
5
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...+ } else {
> + Type *IType = I->getType();
> + Type *VType = getVecType(IType);
> +
> + if (IType->isVectorTy()) {
> + unsigned numElem = cast<VectorType>(IType)->getNumElements();
> + std::vector<Constant*> Mask1(numElem), Mask2(numElem);
> + for (unsigned v = 0; v< numElem; ++v) {
> + Mask1[v] = ConstantInt::get(Type::getInt32Ty(Context), v);
> + Mask2[v] = ConstantInt::get(Type::getInt32Ty(Context), numElem+v);
> + }
> +
> + K1 = new ShuffleVectorInst...
2011 Dec 14
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...Type *IType = I->getType();
> > + Type *VType = getVecType(IType);
> > +
> > + if (IType->isVectorTy()) {
> > + unsigned numElem = cast<VectorType>(IType)->getNumElements();
> > + std::vector<Constant*> Mask1(numElem), Mask2(numElem);
> > + for (unsigned v = 0; v< numElem; ++v) {
> > + Mask1[v] = ConstantInt::get(Type::getInt32Ty(Context), v);
> > + Mask2[v] = ConstantInt::get(Type::getInt32Ty(Context), numElem+v);
> > + }
> > +
> > +...
2011 Nov 23
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Mon, 2011-11-21 at 21:22 -0600, Hal Finkel wrote:
> On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote:
> > Tobias,
> >
> > I've attached an updated patch. It contains a few bug fixes and many
> > (refactoring and coding-convention) changes inspired by your comments.
> >
> > I'm currently trying to fix the bug responsible for causing a compile
2011 Dec 02
0
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
...Type *IType = I->getType();
> > + Type *VType = getVecType(IType);
> > +
> > + if (IType->isVectorTy()) {
> > + unsigned numElem = cast<VectorType>(IType)->getNumElements();
> > + std::vector<Constant*> Mask1(numElem), Mask2(numElem);
> > + for (unsigned v = 0; v< numElem; ++v) {
> > + Mask1[v] = ConstantInt::get(Type::getInt32Ty(Context), v);
> > + Mask2[v] = ConstantInt::get(Type::getInt32Ty(Context), numElem+v);
> > + }
> > +
> > +...
2011 Nov 22
5
[LLVMdev] [llvm-commits] [PATCH] BasicBlock Autovectorization Pass
On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote:
> Tobias,
>
> I've attached an updated patch. It contains a few bug fixes and many
> (refactoring and coding-convention) changes inspired by your comments.
>
> I'm currently trying to fix the bug responsible for causing a compile
> failure when compiling
>