search for: machsuif

Hi there, I have a question on the LLVM internals. Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled assembly) prior register allocation? Does LLVM use infinite (virtual) registers similar to MachSUIF? This is, of course, meant for a given target in contrast to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is possible at this point. Plus: How do things progress towards LLVM following release. Is Oct 31, a probable date for the release? What about LLVM-TV, is it going to...

...urope, and talking from my point of view it is not that necessary. If a backend is to be used you have to do at least the following: do_gen ... with option -target_lib <my_target> do_raga ... this does the register allocation do_fin ... this finalizes code Anyway usually i print out of the MachSUIF IR the information I need in the form of data-dependence graphs. There is no such tool in their 02.07.15 distribution so i have written a small pass to do the job. Interfacing to the SUIF IR (kind of object file format) is somewhat complex. It would need some work to convert between LLVM IR and...

...f view it is not that necessary. > > If a backend is to be used you have to do at least the following: > do_gen ... with option -target_lib <my_target> > do_raga ... this does the register allocation > do_fin ... this finalizes code > > Anyway usually i print out of the MachSUIF IR the information I need in > the form of data-dependence graphs. There is no such tool in their > 02.07.15 distribution so i have written a small pass to do the job. > Interfacing to the SUIF IR (kind of object file format) is somewhat > complex. It would need some work to convert...

--- David Greene <greened at obbligato.org> wrote: > Roman Levenstein wrote: > > The allocator does not handle register aliases and register classes > > correctly, which makes it rather unusable for most architectures. > One > > idea that can be used for improving handling of irregular > architectures > > is described in the "A Generalized Algorithm for

Roman Levenstein wrote: > Yes, the SUIF allocator (or at least one of them) implements the > Smith/Ramsey/Holloway algorithm. This is what I understand by looking > at the coloring reggister allocator code in the SUIF distribution. The > SUIF code of this allocator is not very well commented, but I'm pretty > sure. Do you have a pointer? I'm interested in this algorithm

...looking > > at the coloring reggister allocator code in the SUIF distribution. > The > > SUIF code of this allocator is not very well commented, but I'm > pretty > > sure. > > Do you have a pointer? I'm interested in this algorithm as well. I downloaded the MachSUIF sources from here: http://www.eecs.harvard.edu/hube/software/software.html More precisely, I took this version: 2.02.07.15 Have a look at the color.cpp in the raga subdirectory. This is the implementation of Smith/Ramsey/Holloway algorithm, as far as I understand. -Roman __________________...

On Sun, 3 Apr 2005, Sameer D. Sahasrabuddhe wrote: > On Sat, Apr 02, 2005 at 11:35:30AM -0600, Chris Lattner wrote: > >> On Sat, 2 Apr 2005, Sameer D. Sahasrabuddhe wrote: >>> I want to create a simple map from a Value to the instruction that >>> defines it. Such a map is present inside SchedGraph, but I need it in >>> a much simpler context. >>

On Sat, Apr 02, 2005 at 11:35:30AM -0600, Chris Lattner wrote: > On Sat, 2 Apr 2005, Sameer D. Sahasrabuddhe wrote: > > I want to create a simple map from a Value to the instruction that > > defines it. Such a map is present inside SchedGraph, but I need it in > > a much simpler context. > > Is this in the context of the code generator? No ... I am just trying to feel