Displaying 20 results from an estimated 33 matches for "machinepointerinfo".
2012 Mar 15
2
[LLVMdev] Question about post RA scheduler
Thank you for your suggestions.
I implemented the first approach (provided the byval argument and
offset to MachinePointerInfo) and it seems to have fixed the
instruction ordering problem. It was a lot simpler than initially
expected.
In this particular case, is the user responsible for providing alias
information to MachinePointerInfo to guarantee instructions are
emitted in the correct order? It seems to me that getStor...
2012 Mar 15
0
[LLVMdev] Question about post RA scheduler
On Mar 15, 2012, at 10:22 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Thank you for your suggestions.
>
> I implemented the first approach (provided the byval argument and
> offset to MachinePointerInfo) and it seems to have fixed the
> instruction ordering problem. It was a lot simpler than initially
> expected.
>
> In this particular case, is the user responsible for providing alias
> information to MachinePointerInfo to guarantee instructions are
> emitted in the correct orde...
2012 Mar 13
0
[LLVMdev] Question about post RA scheduler
On Mar 7, 2012, at 11:34 AM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> I filed a bug report (Bug 12205).
> Please take a look when you have time.
>
> Per your suggestion, I also attached a patch which attaches to load or
> store nodes a machinepointerinfo that points to a stack frame object
> when it can infer they are actually reading from or writing to the
> stack. The test that was failing passes if I apply this patch, but I
> doubt this is the right approach, because this will fail if
> InferPointerInfo in SelectionDAG.cpp cannot dis...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
I filed a bug report (Bug 12205).
Please take a look when you have time.
Per your suggestion, I also attached a patch which attaches to load or
store nodes a machinepointerinfo that points to a stack frame object
when it can infer they are actually reading from or writing to the
stack. The test that was failing passes if I apply this patch, but I
doubt this is the right approach, because this will fail if
InferPointerInfo in SelectionDAG.cpp cannot discover a load or stor...
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly.
> if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) {
> return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo());
> } else {
> return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT);
> }
I assume that we need the opposite -
if (.. < 8)
getExtLoad // VT should be MVT::i8, MemVT should be MVT::i1
else
getLoad
- Elena
From:...
2012 Nov 24
2
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
...t<FrameIndexSDNode>(SpillSlot)->getIndex();
> SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(),
> SpillVal.getDebugLoc(),
> SpillVal, SpillSlot,
> MachinePointerInfo::getFixedStack(FI),
> false, false, 0);
> Chain = CurDAG->getLoad(SpillVal.getValueType(), SpillVal.getDebugLoc(),
> Chain, SpillSlot,
> MachinePointerInfo::getFixedStack(FI),
>...
2014 Jul 29
2
[LLVMdev] to lower "write to argument pointer"
...nding to input pointer
SDvalue frindex = Op.getoperand(3);
…
SDValue returnValue = DAG.getNode(myNode1, DL, VT….);
SDValue dstValue = DAG.getNode(myNode2, DL, VT….);
// to save the value to dst pointer, I think I need some call like
SDValue dstOut = DAG.getStore(chain, DL, dstValue, FrameIndex, MachinePointerInfo(), false, false, 0);
“
I have two questions here:
(1) should I return some merges values( returnValue, DstValue) ? or only return returnValue is right? ( the dag dumped out looks better if I return the merged values)
(2) How the FrameIndex should be computed? I use DAG.getFrameIndex((dyn_cast&...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...e need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly.
if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) {
return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo());
} else {
return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT);
}
How do you think about it?
Thanks,
JinGu Kang
On 15/09/2017 18:42, Demikhovsky, Elena wrote:
extends the elements to 8bit and stores them on stack.
Store is responsib...
2018 Apr 16
2
How to create a proper MachineMemOperand?
Hi all,
I met a new problem in the process of my project.
I have got an address by mmap. And I want to build a MachineInstr of
MOV64mr to move a value to the address. But it seems that the
MachinePointerInfo needs a pointer to a Value.
So can I create a MachineMemOperand directly with the address (is a long*)
? Or I need to try some other methods?
Thanks a lot,
Will
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2012 Nov 24
0
[LLVMdev] Fwd: Prevention register promotion at the isel codegen phase
...FrameIndexSDNode>(SpillSlot)->getIndex();
> SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(),
> SpillVal.getDebugLoc(),
> SpillVal, SpillSlot,
>
> MachinePointerInfo::getFixedStack(FI),
> false, false, 0);
> Chain = CurDAG->getLoad(SpillVal.getValueType(), SpillVal.getDebugLoc(),
> Chain, SpillSlot,
> MachinePointerInfo::getFixedStack(FI),
>...
2013 Aug 07
3
[LLVMdev] Address space extension
...ation (if it exists) to do the translation. Thats perhaps not the cleanest implementation, but it would work.
I was going to suggest that an alternative is to pass this information in to the load/store instructions in the backend, but it looks like that information is already available. That is, MachinePointerInfo has a getAddrSpace() method. This could potentially allow you to optimize MachineInstrs using the same knowledge you have here, e.g., constness for addrspace(3) in MachineLICM.
>
>>
>> !address_spaces = !{!0, !1, !2, !3}
>>
>> ; Address space tuple. { address space n...
2012 Oct 26
1
[LLVMdev] Properly handling mem-loc arguments when prologue adjusts FP.
...) == 0) {
StackPtr = DAG.getCopyFromReg(Chain, dl, ARC::SP, getPointerTy());
}
SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset()));
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo(),false, false, 0));
}
...
[2]: LowerFormalArguments
...
if (VA.isRegLoc()) {
// Arguments passed in registers.
const TargetRegisterClass *RC = ARC::CPURegsRegisterClass;
unsigned int Register = MF.addLiveIn(VA.getLocReg(), RC);
EVT RegisterValueType = VA.getLocVT(...
2011 Jul 13
1
[LLVMdev] problems with single byte stores in the arm backend
...ddress
in a new helper function inside ARMISelLowering.cpp
I tried:
SDValue Val = DAG.getConstant(4, MVT::i8);
SDValue Store = DAG.getStore(chain,
dl,
Val,
Addr,
MachinePointerInfo(),
false, false, 0);
This gives me a a legalizer assert for MVT::i8.
If I change it to MVT::i32 the code works but instead of
a single byte store (STRB) I get a word store (STR).
How can I force the width of the store?
Thanks,
Robert
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2018 Apr 17
1
How to create a proper MachineMemOperand?
...ill Lester via llvm-dev <
> llvm-dev at lists.llvm.org>:
> > Hi all,
> > I met a new problem in the process of my project.
> > I have got an address by mmap. And I want to build a MachineInstr of
> MOV64mr
> > to move a value to the address. But it seems that the MachinePointerInfo
> > needs a pointer to a Value.
> > So can I create a MachineMemOperand directly with the address (is a
> long*) ?
> > Or I need to try some other methods?
> > Thanks a lot,
> > Will
> >
> > _______________________________________________
> > LLVM...
2018 Apr 16
0
How to create a proper MachineMemOperand?
....
2018-04-16 16:25 GMT+08:00 Will Lester via llvm-dev <llvm-dev at lists.llvm.org>:
> Hi all,
> I met a new problem in the process of my project.
> I have got an address by mmap. And I want to build a MachineInstr of MOV64mr
> to move a value to the address. But it seems that the MachinePointerInfo
> needs a pointer to a Value.
> So can I create a MachineMemOperand directly with the address (is a long*) ?
> Or I need to try some other methods?
> Thanks a lot,
> Will
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at list...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> extends the elements to 8bit and stores them on stack.
Store is responsible for zero-extend. This is the policy...
- Elena
-----Original Message-----
From: jingu at codeplay.com [mailto:jingu at codeplay.com]
Sent: Friday, September 15, 2017 17:45
To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com
Subject: Re: Question
2013 Jan 18
0
[LLVMdev] llvm backend porting question ,
...UNCTION();
DebugLoc DL;
if (MI != MBB.end()) DL = MI->getDebugLoc();
MachineFunction &MF = *MBB.getParent();MF.dump();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(MVT::i8);
MachineMemOperand *MMO =
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MVT::i8),
MachineMemOperand::MOStore,
MFI.getObjectSize(MVT::i8),
Align);
BuildMI(MBB, MI, DL, get(Picoblaze::STORETOSTACK ));//.addMemOperand(MMO);
if (RC == &Picoblaze::GR8RegClass)
{...
2014 Aug 13
2
[LLVMdev] Pseudo load and store instructions for AArch64
...DAG.getConstant(SrcOff, MVT::i64)));
// Ops.push_back(SrcPtrInfo.getWithOffset(SrcOff));
Ops.push_back(DAG.getConstant(0, MVT::i64));
Loads[i] = DAG.getNode(AArch64::FakeLoad64, dl, VT, Ops);
There seems to be something wrong with pointer information inside getNode() as
llvm::MachinePointerInfo::getAddrSpace() asserts.
I can't find an example of similar instructions to start with, are there any
similar pseudoes already?
Any help would be appreciated, even if someone could confirm that it should
be possible to do and I'm just missing something.
Thanks,
Sergey
2013 Aug 07
0
[LLVMdev] Address space extension
...it exists) to do the translation. Thats perhaps not the cleanest implementation, but it would work.
>
> I was going to suggest that an alternative is to pass this information in to the load/store instructions in the backend, but it looks like that information is already available. That is, MachinePointerInfo has a getAddrSpace() method. This could potentially allow you to optimize MachineInstrs using the same knowledge you have here, e.g., constness for addrspace(3) in MachineLICM.
From here: http://llvm.org/docs/LangRef.html#pointer-type
"The semantics of non-zero address spaces are target-sp...
2012 Dec 11
1
[LLVMdev] Loads/Stores and MachineMemOperand
The code itself makes sense, but I want to know if this breaks any
guarantee made about preserving a Value* in the MachineMemOperand. It
sounds like we're having the same issue. We were using the Value* stored
in the MachineMemOperand to get address space information during assembly
printing. The alternative is carrying around a lot of extra (redundant)
information in the SDAG.
If it is