Displaying 9 results from an estimated 9 matches for "machinememoryoperands".
2009 Jan 20
2
[LLVMdev] HazardRecognizer and RegisterAllocation
...They need some work though;
> the main issue is that there are some places in codegen that don't
> preserve them.
Where are those places? Can they be used in conjunction with
MemoryDependenceAnalysis? e.g. can we write a MachineInstructions-based
memory dependence analysis that uses MachineMemoryOperands?
> Another possibility is to record dependence information from the
> SelectionDAG in MachineInstrs somehow. We don't yet have precise
> memory dependencies in the SelectionDAG, but it would be good to
> fix that too :-).
Agreed.
> This would probably also involve AliasAnalys...
2009 Jan 20
0
[LLVMdev] HazardRecognizer and RegisterAllocation
...ad() || MI->mayStore()) || !MI->memoperands_empty()
to catch most cases. There may not be many places left at
this point.
> Can they be used in conjunction with
> MemoryDependenceAnalysis? e.g. can we write a MachineInstructions-
> based
> memory dependence analysis that uses MachineMemoryOperands?
Right, the existing MemoryDependenceAnalysis works in terms of
LLVM-IR-level Instructions, but yes, it would be possible to
implement the same thing for MachineInstrs, using AliasAnalysis
queries from MachineMemOperands. As of this writing I'm not
prepared to guess whether this would be a goo...
2009 Jan 20
1
[LLVMdev] HazardRecognizer and RegisterAllocation
On Monday 19 January 2009 19:47, Dan Gohman wrote:
> > Can they be used in conjunction with
> > MemoryDependenceAnalysis? e.g. can we write a MachineInstructions-
> > based
> > memory dependence analysis that uses MachineMemoryOperands?
>
> Right, the existing MemoryDependenceAnalysis works in terms of
> LLVM-IR-level Instructions, but yes, it would be possible to
> implement the same thing for MachineInstrs, using AliasAnalysis
> queries from MachineMemOperands. As of this writing I'm not
> prepared to gues...
2009 Jan 20
0
[LLVMdev] HazardRecognizer and RegisterAllocation
On Jan 19, 2009, at 3:38 PM, David Greene wrote:
> On Monday 19 January 2009 16:42, Dan Gohman wrote:
>
>>>> Perhaps you want to do this after register allocation is done.
>>>> Dan is
>>>> developing the post-allocation scheduler. You can try it out.
>>>
>>> Interesting. Can it already be found SVN? I will search the mail
>>>
2009 Jan 19
2
[LLVMdev] HazardRecognizer and RegisterAllocation
On Monday 19 January 2009 16:42, Dan Gohman wrote:
> >> Perhaps you want to do this after register allocation is done. Dan is
> >> developing the post-allocation scheduler. You can try it out.
> >
> > Interesting. Can it already be found SVN? I will search the mail
> > archive
> > later, if not.
>
> Yes, it is in SVN. It's new, and so far
2019 Nov 14
2
[MCDisassembler] Identifying instructions that definitely access memory
[ This question has already been asked in lldb-dev (see attached emails), however it was suggested that I should forward the question to llvm-dev, since it is more relevant to MC Disassembler than LLDB. ]
Hello,
I am looking for a way to track memory stores and save both the old and the new value of the memory location being modified using LLDB, as described below:
1. Recognize the
2018 Nov 10
3
[RFC] Tablegen-erated GlobalISel Combine Rules
...using MIR came up, we liked the fact that it matched the existing serialization format which makes it easy to turn a specific example from the compiler output into a combine rule and avoid the need for another representation for instructions. We also liked the way it dealt with the difficult cases, MachineMemoryOperands, subregs, etc. and also that it wasn't a new syntax or parser (although it make require modifications to the existing one). It also looked like it be convenient for a tool like Alive (https://www.cs.utah.edu/~regehr/papers/pldi15.pdf) although we didn't really explore that particular though...
2018 Nov 12
3
[RFC] Tablegen-erated GlobalISel Combine Rules
...using MIR came up, we liked the fact that it matched the existing serialization format which makes it easy to turn a specific example from the compiler output into a combine rule and avoid the need for another representation for instructions. We also liked the way it dealt with the difficult cases, MachineMemoryOperands, subregs, etc. and also that it wasn't a new syntax or parser (although it make require modifications to the existing one). It also looked like it be convenient for a tool like Alive (https://www.cs.utah.edu/~regehr/papers/pldi15.pdf) although we didn't really explore that particular though...
2018 Nov 09
5
[RFC] Tablegen-erated GlobalISel Combine Rules
Hi All,
I've been working on the GlobalISel combiner recently and I'd like to share the plan for how Combine Rules will be defined in GlobalISel and solicit feedback on it.
This email ended up rather long so:
TL;DR: We're planning to define GlobalISel Combine Rules using MIR syntax with a few bits glued on to interface with the algorithm and escape into C++ when we need to.