search for: machineintr

...strs. Also, such a pass will need to work with > virtual registers as you'll need an unlimited supply of temporary > variables. In essence, you'll be undoing register allocation. > > Can you describe why you want to put MachineInstrs into SSA form? I > suspect that putting MachineIntrs back into SSA form is not what you want > to do. > > Regards, > > John Criswell > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140923/c46d4dc3/attachment.html>

Hi, I'm wondering how I can convert "register allocated" code back to SSA form. I realized from MachineRegisterInfo.h that a function leaves SSA form only once and cannot be taken back to it. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140923/0124addd/attachment.html>

Can someone explain what MCInst is vs. MachineIntr? I'm porting some patches we have here that affect MachineInstrs and am wondering whether I need to make similar changes in MCInst. Why do we have two machine instruction representations? -Dave

Hi, Recently, I am working on some information collection on the machine instruction (MachineInstr) level. But, sometimes, I need check the corresponding IR level instruction of the a machine instruction. When visiting a machine instruction which is a call (MachineInstr::isCall()), I need to check the arguments of this call site. I know that the CallSite class provides good facility for this

On Jul 9, 2009, at 5:34 PM, David Greene wrote: > Can someone explain what MCInst is vs. MachineIntr? Sure. MCInst is designed to be part of the "MC" set of libraries, which is stuff dealing with machine code. We're building a suite of assemblers and disassemblers out of this. MCInst is integral to this plan. For an assembler you have two pieces: 1. "Recognize" an...

On Friday 13 November 2009 15:17, you wrote: > > Are these known to be broken right now? I get failure when using either. > > > > $ llc -march=arm -print-machineinstrs hw.bc > > Seems due to David's patches. Ok, it's faulting in SlotTracker with what looks like a bad Function. One of the Argument values is corrupted. I'm not abdicating responsibility, but at

...arly-clobber register so that the allocator will not use the same register for it as for Rm or Rn. The syntax is simple: contraint-list: constraint-list ',' constraint | constraint constraint: '@early' operand | operand '=' operand operand: '$' identifier MachineIntr::addOperand() checks the target instruction description for the constraint when adding register operands and sets IsEarlyClobber if it's present. For a usage example, I've included in the patch the modification to use the constraint for the STREX ARM instruction. Thoughts? Thanks i...

...opcode, e.g., ADD, COPY. - IRTranslator: Translate LLVM IR to (G) MachineInstr. - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. - Select: Translate the remaining (G) MachineInstr to MachineIntr. ** Implications ** As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: - Need to remember FastMath flags for each MachineInstr. - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16, etc. - Extend the MachineRegisterInfo...

...COPY. > - IRTranslator: Translate LLVM IR to (G) MachineInstr. > - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. > - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. > - Select: Translate the remaining (G) MachineInstr to MachineIntr. > > > > ** Implications ** > > As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: > - Need to remember FastMath flags for each MachineInstr. > - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16,...

...COPY. > - IRTranslator: Translate LLVM IR to (G) MachineInstr. > - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. > - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. > - Select: Translate the remaining (G) MachineInstr to MachineIntr. > > > > ** Implications ** > > As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: > - Need to remember FastMath flags for each MachineInstr. > - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16,...

...> - IRTranslator: Translate LLVM IR to (G) MachineInstr. > - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. > - RegBankSelect: Assign virtual register with size to virtual register > with Register Bank. > - Select: Translate the remaining (G) MachineInstr to MachineIntr. > > > > ** Implications ** > > As part of the bring-up of the prototype, we need to extend some of the > core MachineInstr-level APIs: > - Need to remember FastMath flags for each MachineInstr. > - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16...

...COPY. > - IRTranslator: Translate LLVM IR to (G) MachineInstr. > - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. > - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. > - Select: Translate the remaining (G) MachineInstr to MachineIntr. > > > > ** Implications ** > > As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: > - Need to remember FastMath flags for each MachineInstr. > - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16,...

...COPY. > - IRTranslator: Translate LLVM IR to (G) MachineInstr. > - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. > - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. > - Select: Translate the remaining (G) MachineInstr to MachineIntr. > > > > ** Implications ** > > As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: > - Need to remember FastMath flags for each MachineInstr. > - Need to know the type of each MachineInstr. We don’t want ADD8, ADD16,...

...IRTranslator: Translate LLVM IR to (G) MachineInstr. >> - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. >> - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. >> - Select: Translate the remaining (G) MachineInstr to MachineIntr. >> >> >> >> ** Implications ** >> >> As part of the bring-up of the prototype, we need to extend some of the core MachineInstr-level APIs: >> - Need to remember FastMath flags for each MachineInstr. >> - Need to know the type of each MachineI...