search for: machineinstrs

On Wed, Sep 19, 2007 at 05:24:12PM +1000, Emil Mikulic wrote: > http://goanna.cs.rmit.edu.au/~emil/llvm2.1-check-debug.txt Here's an ARM test that cores: $ llvm-as < /home/emil/ll/llvm-2.1/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll | llc -march=arm -mattr=+v6,+vfp2 Segmentation fault (core dumped) $ gdb `which llc` llc.core [...] (gdb) where #0 0x0853d606 in

I'm trying to clone a MachineInstr in the AsmPrinter::EmitInstruction, Here is the code: void EsenciaAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineFunction *MF = MI->getParent()->getParent(); MachineInstr *CloneMI = MF->CloneMachineInstr(MI); ... ... } The problem is that MF is a const and CloneMachineInstr expects a non-const. Does anybody know if there is

A question about how the memory of object in LLVM are managed. I dived in some source files but still don't have any idea how the memory of MachineInstr object are managed. It doesn't look like reference counting. I'm writing an instruction scheudling code, the new order of MachineInstr* in a MachineBasicBlock is stored in a "schedule". All MachineInstr* in

Hello, I'm working on integrating the MachinePipeliner.cpp pass into our VLIW backend, and so far we've managed to get it working with some nice speedups. Unlike Hexagon however, our backend doesn't generate hardware loop instructions and so all our loops are a combination of induction variables, comparisons and branches. So when it came to implementing reduceLoopCount for our

Hi, Recently, I am working on some information collection on the machine instruction (MachineInstr) level. But, sometimes, I need check the corresponding IR level instruction of the a machine instruction. When visiting a machine instruction which is a call (MachineInstr::isCall()), I need to check the arguments of this call site. I know that the CallSite class provides good facility for this

I'm working on a custom VLIW (we call it Escala). At the moment I'm trying to implement EscalaAsmPrinter::EmitInstruction(const MachineInstr *MI). I'm trying to clone an instruction and this produces and error. Below are the code as well as error: void EscalaAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineFunction *MF = MI->getParent()->getParent();

On Tue, Sep 18, 2007 at 06:41:38PM +1000, Emil Mikulic wrote: > The "make check" produced: > === Summary === > > # of expected passes 2209 > # of unexpected failures 41 > # of expected failures 5 > gmake[1]: *** [check-local] Error 1 > gmake[1]: Leaving directory `/home/emil/ll/objdir-llvm/test' > gmake: ***

Is this the same issue as PR1686? If so, please add to it. What kind of host machine are you using? Thanks, Evan On Sep 19, 2007, at 12:45 AM, Emil Mikulic wrote: > On Wed, Sep 19, 2007 at 05:24:12PM +1000, Emil Mikulic wrote: >> http://goanna.cs.rmit.edu.au/~emil/llvm2.1-check-debug.txt > > Here's an ARM test that cores: > > $ llvm-as <

...or<MachineInstr*> > In this map, its keyvalue is IR instruction pointer, and its second value is a container which is composed of MachineInstr lowering by its keyvalue. For example: IR Instruction %0 = load i32* getelementptr inbounds ([6 x i32]* @a, i32 0, i32 5), align 4, !tbaa !0 Two MachineInstrs lowed by this IR are shown following and used as This IR's second value in the map %vreg0<def> = MOVi32 <ga:@a>; GPR:%vreg0 %vreg1<def> = LOADi32 %vreg0, 20, pred:14, preg:%noreg; mem:LD4[getelementptr inbounds ([6 x i32]* @a, i32 0, i32 5)] (tbaa !="int") GPR:%vreg1...

Hello. I am having difficulties to bundle MachineInstr instructions, before register allocation (RA). More exactly, I registered a simple pass in addPreRegAlloc() that is trying to create bundles. I see that it is written at http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles: <<Packing / bundling of MachineInstr’s should be done as part of the register

Hi all, I have learned about LLVM backend passes. LLVM IR changes its format four times until final output assembly/object through SelectionDAG, MachineInstr, MCInst. MCInst format layer seems to be called as "MC layer" officially. What about MachineInstr format layer? It seems to be called as "MI layer", is it officially? Please tell me there is good name for representing

Dear All, I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment directive to the assembler) if it causes a specific sequence of bytes to be generated at a specific alignment. The goal is to ensure that sequences of

I keep getting this error upon building: > Linking CXX executable ../../bin/opt > ../../lib/libLLVMTarget.so: error: undefined reference to > 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData > const*, llvm::MachineInstr const*) const' > ../../lib/libLLVMTarget.so: error: undefined reference to >

Hi all, Two days ago MachineBasicBlock got ilistified. What does this mean and how does it affect you? Read on. MachineBasicBlock used to have a std::vector<MachineInstr*> to represent the instructions it constisted of. This representation has the following problems: 1) O(n) insertions/removals to/from anywhere but the end of a basic block (removals are very comomn in peephole

Dear LLVMers, I am trying to fold memory operands in the way that is done in RegAllocLocal.cpp, or in LiveIntervalAnalysis.cpp, but I am getting errors that I don't know how to fix. Could someone tell me which steps should I take in order to correctly fold memory operands? The code that I am using is: const TargetMachine & target_machine = this->machine_function->getTarget();

.... ** High Level Prototype Design ** As shown in the talk, the expected pipeline for the prototype is: LLVM IR -> IRTranslator -> Generic (G) MachineInstr -> Legalizer -> RegBankSelect -> Select -> MachineInstr Where: - Terms in bold are intermediate representations. - Generic MachineInstrs are machine instructions with a generic opcode, e.g., ADD, COPY. - IRTranslator: Translate LLVM IR to (G) MachineInstr. - Legalizer: Legalize illegal (G) MachineInstr to legal (G) MachineInstr. - RegBankSelect: Assign virtual register with size to virtual register with Register Bank. - Select: Tran...

Chris Lattner wrote: > There are a couple of ways to do this. Is your scheduler a prepass > scheduler (before regalloc) or a post-pass scheduler (after regalloc)? it is a post-pass scheduler, which operates on MachineInstrs. we need to run it after register allocation to hide latencies of spill code, prolog, and epilog. > If you want to extract maximal parallelism, I assume you want a prepass > scheduler. In that case, you should look into the SelectionDAG based > schedulers, which do have alias information...

...'t see a method for finding > the exact bytes that would be emitted from the MachineInstr. Is there > a way to do this in the MachineFunctionPass/MachineInstr > infrastructure, or do I need to use something like the MC classes? > As I recall (I haven't played this deep with MachineInstrs for close to a year), it's not necessarily knowable what the length is or the exact bytes that would be emitted since some of them depend on information not known until the final assembly emission pass. An example here is the x86 jmp instruction: the choice between near and long jumps (and...

I'm getting to the point where I want to contribute some more MachineInstr comment support for things like spills. As we've discussed before, we don't have all of the information available in AsmPrinter to synthesize the kind of comments that can be helpful for debugging performance issues with register allocators (our primary use for these kinds of comments). In order to get this

On Jun 8, 2012, at 12:52 PM, Marc J. Driftmeyer <mjd at reanimality.com> wrote: > I keep getting this error upon building: > >> Linking CXX executable ../../bin/opt >> ../../lib/libLLVMTarget.so: error: undefined reference to 'llvm::TargetInstrInfo::getNumMicroOps(llvm::InstrItineraryData const*, llvm::MachineInstr const*) const' >>