Displaying 20 results from an estimated 20 matches for "lwzx".
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lwz
2013 Nov 19
2
[LLVMdev] [3.4 branch] PPC64 regressions
...s] stw 4, 4(7)
[ 3468s] ^
[ 3467s]
/home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/anon_aggr.ll:75:13:
error: expected string not found in input
[ 3467s] ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
[ 3467s] ^
[ 3467s] <stdin>:40:2: note: scanning from here
[ 3467s] lwzx r6, r7, r6
[ 3467s] ^
[ 3467s] <stdin>:40:2: note: with variable "REGSP" equal to "1"
[ 3467s] lwzx r6, r7, r6
[ 3467s] ^
[ 3467s] <stdin>:65:3: note: possible intended match here
[ 3467s] stw r9, 48(r1)
[ 3467s] ^
[ 3466s]
/home/abuild/rpmbuild/BUILD/llvm/tes...
2013 Nov 19
0
[LLVMdev] [3.4 branch] PPC64 regressions
...>
> [ 3467s]
> /home/abuild/rpmbuild/BUILD/llvm/test/CodeGen/PowerPC/anon_aggr.ll:75:13:
> error: expected string not found in input
> [ 3467s] ; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])
> [ 3467s] ^
> [ 3467s] <stdin>:40:2: note: scanning from here
> [ 3467s] lwzx r6, r7, r6
> [ 3467s] ^
> [ 3467s] <stdin>:40:2: note: with variable "REGSP" equal to "1"
> [ 3467s] lwzx r6, r7, r6
> [ 3467s] ^
> [ 3467s] <stdin>:65:3: note: possible intended match here
> [ 3467s] stw r9, 48(r1)
> [ 3467s] ^
>
>
>...
2004 May 09
0
[LLVMdev] Testing LLVM on OS X
...pb":
> mflr r2
> mtlr r5
> addis r4,r2,ha16(L_Array$non_lazy_ptr-"L00000000001$pb")
> li r2,0
> lwz r9,lo16(L_Array$non_lazy_ptr-"L00000000001$pb")(r4)
> li r4,1000
> mtctr r4
> L9:
> lwzx r7,r2,r9 ; load
> add r6,r7,r3 ; add
> stwx r6,r2,r9 ; store
> addi r2,r2,4 ; Increment pointer
> bdnz L9 ; Decrement count register, branch while not zero
> blr
>
> This is nice code,...
2016 Jan 26
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...> 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> > > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > > > }
> > > > P0 | P1 | P2 ;
> > > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > > > xor r7,r6,r6 | lwsync | lwsync ;
> > > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > > > lwz r8,0(r3) | | ;
> > > >
> > > > exists
> > > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
> > >
> > > That really hurts. Assuming that the "assert(!(z=2))" is actually there...
2016 Jan 26
2
[v3,11/41] mips: reuse asm-generic/barrier.h
...> 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> > > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > > > }
> > > > P0 | P1 | P2 ;
> > > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > > > xor r7,r6,r6 | lwsync | lwsync ;
> > > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > > > lwz r8,0(r3) | | ;
> > > >
> > > > exists
> > > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
> > >
> > > That really hurts. Assuming that the "assert(!(z=2))" is actually there...
2016 Jan 26
5
[v3,11/41] mips: reuse asm-generic/barrier.h
...; > *)
> > {
> > 0:r1=x; 0:r2=y; 0:r3=z;
> > 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > }
> > P0 | P1 | P2 ;
> > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > xor r7,r6,r6 | lwsync | lwsync ;
> > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > lwz r8,0(r3) | | ;
> >
> > exists
> > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
>
> That really hurts. Assuming that the "assert(!(z=2))" is actually there
> to constrain the coherence order of z to be {0->1-&...
2016 Jan 26
5
[v3,11/41] mips: reuse asm-generic/barrier.h
...; > *)
> > {
> > 0:r1=x; 0:r2=y; 0:r3=z;
> > 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > }
> > P0 | P1 | P2 ;
> > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > xor r7,r6,r6 | lwsync | lwsync ;
> > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > lwz r8,0(r3) | | ;
> >
> > exists
> > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
>
> That really hurts. Assuming that the "assert(!(z=2))" is actually there
> to constrain the coherence order of z to be {0->1-&...
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
.... lwsync lwsync
Ry=0 Wz=1 Wx=1
Rz=1
assert(!(z=2))
Forbidden by ppcmem, allowed by herd.
*)
{
0:r1=x; 0:r2=y; 0:r3=z;
1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
}
P0 | P1 | P2 ;
lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
xor r7,r6,r6 | lwsync | lwsync ;
lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
lwz r8,0(r3) | | ;
exists
(z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
.... lwsync lwsync
Ry=0 Wz=1 Wx=1
Rz=1
assert(!(z=2))
Forbidden by ppcmem, allowed by herd.
*)
{
0:r1=x; 0:r2=y; 0:r3=z;
1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
}
P0 | P1 | P2 ;
lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
xor r7,r6,r6 | lwsync | lwsync ;
lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
lwz r8,0(r3) | | ;
exists
(z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
2004 May 04
0
[LLVMdev] Testing LLVM on OS X
On Tue, 4 May 2004, Patrick Flanagan wrote:
> I was able to run through all the C/C++ benchmarks in SPEC using LLVM.
> I'm on OS X 10.3.3. I did a quick comparison between LLVM (latest from
> CVS as of 4/27) and gcc 3.3 (Apple's build 20030304). For simplicity's
> sake, the only flag I used was -O3 for each compiler and I was using
> the C backend to generate native
2004 May 04
2
[LLVMdev] Testing LLVM on OS X
I was able to run through all the C/C++ benchmarks in SPEC using LLVM.
I'm on OS X 10.3.3. I did a quick comparison between LLVM (latest from
CVS as of 4/27) and gcc 3.3 (Apple's build 20030304). For simplicity's
sake, the only flag I used was -O3 for each compiler and I was using
the C backend to generate native code for PPC.
Most of the LLVM results were close to gcc
2016 Jan 26
0
[v3,11/41] mips: reuse asm-generic/barrier.h
...1=x; 0:r2=y; 0:r3=z;
> > > 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > > }
> > > P0 | P1 | P2 ;
> > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > > xor r7,r6,r6 | lwsync | lwsync ;
> > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > > lwz r8,0(r3) | | ;
> > >
> > > exists
> > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
> >
> > That really hurts. Assuming that the "assert(!(z=2))" is actually there
> > to constrain the co...
2016 Jan 27
0
[v3,11/41] mips: reuse asm-generic/barrier.h
...1:r4=1;
> > > > > 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> > > > > }
> > > > > P0 | P1 | P2 ;
> > > > > lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> > > > > xor r7,r6,r6 | lwsync | lwsync ;
> > > > > lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> > > > > lwz r8,0(r3) | | ;
> > > > >
> > > > > exists
> > > > > (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
> > > >
> > > > That really hurts. Assuming that the "assert(!...
2001 Oct 30
0
vorbis-tools segfault on aix 4.3
...aix4.3.3.0 with
gcc-2.95.2 (no other gnu utils used for building, I suspect this
being the cause for the segfaults I get).
Running ${HOME}/vorbis/usr/bin/oggenc test.wav gives me:
Segmentation fault in codec_setup_partialcopy at 0xd10a72c8
0xd10a72c8 (codec_setup_partialcopy+0x100) 7d5b002e lwzx r10,r27,r0
(output from dbx - the only debugger I found so far here)
and
${HOME}/vorbis/usr/bin/ogg123 test1.ogg says:
Segmentation fault in glink.realloc at 0xd119e364 ($t1)
0xd119e364 (realloc+0x58) 800c0000 lwz r0,0x0(r12)
The first one appears to be in the `time backend settings...
2015 Feb 24
2
[LLVMdev] Question about shouldMergeGEPs in InstructionCombining
On Mon, Feb 23, 2015 at 2:17 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
> > From: "Francois Pichet" <pichet2000 at gmail.com>
> > To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>
> > Sent: Sunday, February 22, 2015 5:34:11 PM
> > Subject: [LLVMdev] Question about shouldMergeGEPs in
2016 Jan 25
0
[v3,11/41] mips: reuse asm-generic/barrier.h
...> Forbidden by ppcmem, allowed by herd.
> *)
> {
> 0:r1=x; 0:r2=y; 0:r3=z;
> 1:r1=x; 1:r2=y; 1:r3=z; 1:r4=1;
> 2:r1=x; 2:r2=y; 2:r3=z; 2:r4=1; 2:r5=2;
> }
> P0 | P1 | P2 ;
> lwz r6,0(r1) | stw r4,0(r2) | stw r5,0(r3) ;
> xor r7,r6,r6 | lwsync | lwsync ;
> lwzx r7,r7,r2 | stw r4,0(r3) | stw r4,0(r1) ;
> lwz r8,0(r3) | | ;
>
> exists
> (z=2 /\ 0:r6=1 /\ 0:r7=0 /\ 0:r8=1)
That really hurts. Assuming that the "assert(!(z=2))" is actually there
to constrain the coherence order of z to be {0->1->2}, then I think that
this test...
2004 May 04
6
[LLVMdev] Testing LLVM on OS X
...uot;L00000000001$pb"
"L00000000001$pb":
mflr r2
mtlr r5
addis r4,r2,ha16(L_Array$non_lazy_ptr-"L00000000001$pb")
li r2,0
lwz r9,lo16(L_Array$non_lazy_ptr-"L00000000001$pb")(r4)
li r4,1000
mtctr r4
L9:
lwzx r7,r2,r9 ; load
add r6,r7,r3 ; add
stwx r6,r2,r9 ; store
addi r2,r2,4 ; Increment pointer
bdnz L9 ; Decrement count register, branch while not zero
blr
This is nice code, good GCC. :)
Okay, LLVM currentl...
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
On Fri, Jan 15, 2016 at 10:13:48AM +0100, Peter Zijlstra wrote:
> On Fri, Jan 15, 2016 at 09:55:54AM +0100, Peter Zijlstra wrote:
> > On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> > > So smp_mb() provides transitivity, as do pairs of smp_store_release()
> > > and smp_read_acquire(),
> >
> > But they provide different grades of
2016 Jan 15
2
[v3,11/41] mips: reuse asm-generic/barrier.h
On Fri, Jan 15, 2016 at 10:13:48AM +0100, Peter Zijlstra wrote:
> On Fri, Jan 15, 2016 at 09:55:54AM +0100, Peter Zijlstra wrote:
> > On Thu, Jan 14, 2016 at 01:29:13PM -0800, Paul E. McKenney wrote:
> > > So smp_mb() provides transitivity, as do pairs of smp_store_release()
> > > and smp_read_acquire(),
> >
> > But they provide different grades of
2015 Feb 25
2
[LLVMdev] Question about shouldMergeGEPs in InstructionCombining
...: # %for.body
> # =>This Inner Loop Header:
> Depth=1
> slw 8, 5, 4
> ld 9, .LC1 at toc@l(7)
> addi 5, 5, 4
> add 8, 8, 6
> extsw 8, 8
> sldi 8, 8, 2
> lwzx 8, 9, 8
> addi 9, 3, 16
> stw 8, 0(3)
> mr 3, 9
> bdnz .LBB0_1
>
> there are two things wrong here, first:
>
> ld 9, .LC1 at toc@l(7)
>
> this load is loop invariant, and should be hoisted (but was not).
The problem of the non-hoisted TOC load was a backend de...