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...happen and why was it changed? Regards Jocke Example(sorry, this is a bit long): ls -l /proc/11026 total 0 dr-xr-xr-x 3 root root 0 Oct 25 10:39 ./ dr-xr-xr-x 206 root root 0 Jun 29 12:00 ../ -r--r--r-- 1 root root 0 Oct 25 11:40 cmdline lrwxrwxrwx 1 root root 0 Oct 25 11:40 cwd -> // -r-------- 1 root root 0 Oct 25 11:40 environ lrwxrwxrwx 1 root root 0 Oct 25 11:40 exe -> /usr/local/samba2.2.3/sbin/smbd* dr-x------ 2 root root 0 Oct 25 10:39 fd/ -r--r--r--...

Hi. I tried for some time to reproduce the "Login process died too early issue". It seems related to when the system run out of file descriptors, to force the issue i forwarded 3k of messages trough the server(using thunderbird). I also tried with my usual mail application - mail.app, but no luck there. Aug 26 18:46:36 soekris postfix/cleanup[14739]: fatal: accept

...hpad.net/ubuntu/+source/klibc/+bug/527720 --- klibc-1.5.20.orig/usr/klibc/arch/arm/vfork.S +++ klibc-1.5.20/usr/klibc/arch/arm/vfork.S @@ -25,7 +25,11 @@ vfork: ldrcs r3, 1f mvncs r0, #0 strcs r2, [r3] +#if defined (___ARM_ARCH_4T__) || defined (__ARM_ARCH_4__) mov pc, lr +#else + bx lr +#endif .balign 4 1: @@ -49,7 +53,11 @@ vfork: str r2, [r1] neg r0, r0 1: +#if defined (___ARM_ARCH_4T__) || defined (__ARM_ARCH_4__) mov pc, lr +#else + bx lr +#endif .balign 4 2: --- klibc-1.5.20.orig/usr/klibc/arch/arm/setjmp.S +++ klibc-1.5.20/usr/klibc/arch/arm/...

...patterns it would be useful on. You've mentioned matrix multiply - how does > this pass alter the IR? Here's before and after IR for the matrix_mul example. Notice the two bitcasts %1 and %2 generated in the for.cond.cleanup block. The L.E.V pass converts these to scevgep values that already exist. *** Code after LSR *** ; Function Attrs: nounwind optsize define void @matrix_mul(i32 %Size, i32* nocapture %Dst, i32* nocapture readonly %Src, i32 %Val) #0 { entry: %cmp.25 = icmp eq i32 %Size, 0 br i1 %cmp.25, label %for.cond.cleanup, label %for.body.4.lr.ph.preheader for.body.4...

On Jan 9, 2009, at 11:37 AMPST, Evan Cheng wrote: > This looks like a bar in ARMInstrInfo.td: > > BX_RET should be marked with Uses = [LR] since it uses LR. However, > this won't work if there is a call BL before the BX_RET. BL is marked > as if it implicitly define LR. So we'll end up with this (hello world > example): PPC has the call (BL) marked with Defs=LR and the return (BLR) marked with Uses=LR, and works AFA...

.../1/7 Evan Cheng <evan.cheng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > > > As you can see, PrologEpilogInserter has inserted at the beginning > of the function some code for manipulation of the frame pointer and > this inserted code uses the LR register. > As far as I understand, ARMRegisterInfo.td should exclude the LR > register from the set of allocatable registers for functions that > require frame pointer manipulation. > But currently it is not the case, or? > > No, LR is not the frame pointer. It's the link...

This looks like a bar in ARMInstrInfo.td: BX_RET should be marked with Uses = [LR] since it uses LR. However, this won't work if there is a call BL before the BX_RET. BL is marked as if it implicitly define LR. So we'll end up with this (hello world example): Live Ins: %LR %R7 %SP<def> = SUBri %SP<kill>, 8, 14, %reg0, %reg0 STR %LR&lt...

Hello, I have used the following data to draw my barplot: BL LR Q 36.35 1.00 1.92 36.91 4.00 0.00 25.70 6.00 0.00 34.38 3.00 1.92 05.32 0.50 0.00 BL<-c(36.35, 36.91, 25.70, 34.38, 05.32) LR<-c(1.00, 4.00, 6.00, 3.00, 0.50) Q<-<(1.92, 0.00, 0.00, 1.92, 0.00) barplot(dt$LR, main='LR Value', col='orange'...

...ed register coalescing graph coloring allocator and try to test it with all backends available currently in LLVM. Initial tests with most of the backends are successful. It turned out that my allocator triggers a specific assertion in the RegScavenger and only for the ARM target. It looks like the LR register is used for frame pointer related things, but it is STILL available for register allocation according to the ARMRegisterInfo.td: def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R12, R11,...

...tion for the algorithm used? Is it based on a published paper? The input IR I have is the following: define <4 x float> @structurizer_test(<4 x float> %inp.coerce) { %1 = extractelement <4 x float> %inp.coerce, i32 0 %2 = fcmp ogt float %1, 0.000000e+00 br i1 %2, label %.lr.ph.i, label %._crit_edge.i .lr.ph.i: ; preds = %7, %0 %i.03.i = phi float [ %8, %7 ], [ 0.000000e+00, %0 ] %ret.02.i = phi <4 x float> [ %5, %7 ], [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %0 ] %3 =...

.../13 Evan Cheng <echeng at apple.com>: > > On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: > >> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >> Predecessors according to CFG: 0x8fdac90 (#0) >> %R0<def> = MOVi 0, 14, %reg0, %reg0 >> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >> [0x8fc2d68 + 0] >> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >> BX_RET 14, %reg0 > > Ok, ignore my earlier em...

...> ; Function Attrs: ssp uwtable > define { <2 x float>, float } @_Z18sampleNullOperator5PointS_(i64 > %pmin.coerce0, i32 %pmin.coerce1, i64 %pmax.coerce0, i32 %pmax.coerce1) #0 > { > %1 = icmp slt i32 %pmin.coerce1, %pmax.coerce1 > br i1 %1, label %.lr.ph35.i, label %_ZN15SamplingClosureD1Ev.exit > > .lr.ph35.i: ; preds = %0 > %2 = lshr i64 %pmin.coerce0, 32 > %3 = trunc i64 %2 to i32 > %4 = lshr i64 %pmax.coerce0, 32 > %5 = trunc i64 %4 to i32 > %6...

...gt; >>> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >>> >>>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>>> Predecessors according to CFG: 0x8fdac90 (#0) >>>> %R0<def> = MOVi 0, 14, %reg0, %reg0 >>>> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >>>> [0x8fc2d68 + 0] >>>> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >>>> BX_RET 14, %reg0 >>...

Hi, Since almost all operations in the FUSE low-level API identify files by inode number, I''ve been using zfs_zget() to get the corresponding znode/vnode in order to call the corresponding VFS function in zfs_vnops.c. However, there are some cases when zfs_zget() behaves slightly different than I need: 1) If zp->z_unlinked != 0 then zfs_zget() returns ENOENT. I need it to return

...%4 = icmp ult i32 %2, %3 br i1 %4, label %.lr.ph3, label %._crit_edge...

If the vgic needs to inject a virtual irq into the guest, but no free LR registers are available, add the irq to a list and return. Whenever an LR register becomes available we add the queued irq to it and remove it from the list. We use the gic lock to protect the list and the bitmask. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> --- xen...

...c.c519528374e3101a61791cf5a0ad1aae.0 Via: SIP/2.0/UDP 172.20.40.6;branch=z9hG4bK56ac.2ecd3532ae51c927dabcc6e27eaa4cbe.0 Via: SIP/2.0/UDP 217.10.68.137;branch=z9hG4bK56ac.73e224299594933979fdfb5b036e6563.0 Via: SIP/2.0/UDP 217.10.77.115:5060;branch=z9hG4bK7b31f031 Record-Route: <sip:217.10.79.9;lr;ftag=as02fa8fcc> Record-Route: <sip:172.20.40.6;lr> Record-Route: <sip:217.10.68.137;lr;ftag=as02fa8fcc> From: "02363361779" <sip:02363361779 at sipgate.de>;tag=as02fa8fcc To: <sip:2636146e0 at sipgate.de> Call-ID: 370c0afa42c39f3d4ba96d7b0c1e7d49 at sipgate.de...

...r (possibly even worse): define void @matrix_mul(i32 %Size, i32* nocapture %Dst, i32* nocapture readonly %Src, i32 %Val) { entry: %Src12 = bitcast i32* %Src to i8* %Dst14 = bitcast i32* %Dst to i8* %cmp.25 = icmp eq i32 %Size, 0 br i1 %cmp.25, label %for.cond.cleanup, label %for.body.4.lr.ph.preheader for.body.4.lr.ph.preheader: ; preds = %entry %0 = shl i32 %Size, 2 br label %for.body.4.lr.ph for.body.4.lr.ph: ; preds = %for.body.4.lr.ph.preheader, %for.cond.cleanup.3 %lsr.iv17 = phi i32 [ %Size, %for.body.4.lr.ph.pre...

...at apple.com>: >> >> On Jan 7, 2009, at 2:48 AM, Roman Levenstein wrote: >> >>> bb368: 0x8fdad00, LLVM BB @0x8fc2c98, ID#1: >>> Predecessors according to CFG: 0x8fdac90 (#0) >>> %R0<def> = MOVi 0, 14, %reg0, %reg0 >>> *** STR %LR<kill>, %R0<kill>, %reg0, 0, 14, %reg0, Mem:ST(4,4) >>> [0x8fc2d68 + 0] >>> %LR<def> = LDR <fi#0>, %reg0, 0, 14, %reg0 >>> %SP<def> = ADDri %SP<kill>, 4, 14, %reg0, %reg0 >>> BX_RET 14, %reg0 >> >> Ok,...

...matrix multiply - how > does > >> this pass alter the IR? > > > > Here's before and after IR for the matrix_mul example. Notice the two > > bitcasts %1 and %2 generated in the for.cond.cleanup block. The L.E.V > > pass converts these to scevgep values that already exist. > > > > *** Code after LSR *** > > > > ; Function Attrs: nounwind optsize > > define void @matrix_mul(i32 %Size, i32* nocapture %Dst, i32* nocapture > > readonly %Src, i32 %Val) #0 { > > entry: > > %cmp.25 = icmp eq i32 %Size, 0 > >...