Displaying 18 results from an estimated 18 matches for "lowleveltype".
2017 Apr 03
5
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...running on Cortex-A57 AArch64 Linux.
I saw one assertion failure in GlobalISel, see http://bugs.llvm.org/show_bug.cgi?id=32471. This is in a program compiled at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for that program). The root cause of the failure seems to be due to LowLevelType not supporting vectors of pointers. I think this demonstrates that for correctness, we should be trying to test more than -O0, or even more than just LLVM-IR produced by clang, as other front-ends could run into this even at -O0.
Due to this assertion failure and the infrastructure I used, the num...
2019 Mar 11
4
GlobalISel: Ambiguous intrinsic semantics problem
Hi GlobalISel interested parties,
A recent bug report (https://bugs.llvm.org/show_bug.cgi?id=40968) on AArch64 exposed a problem with our modeling of intrinsic semantics when dealing with type overloaded calls. The crux of the matter is that because GlobalISel’s LowLevelTypes only carry size and vector layout information, and not any information about whether a type is integer or fp, we lose information during IR translation of type overloaded intrinsics.
Most of the time, we don’t run into this issue because the generic opcodes distinguish between fp and int operatio...
2019 Mar 11
2
GlobalISel: Ambiguous intrinsic semantics problem
...>>
>> A recent bug report (https://bugs.llvm.org/show_bug.cgi?id=40968 <https://bugs.llvm.org/show_bug.cgi?id=40968>) on AArch64 exposed a problem with our modeling of intrinsic semantics when dealing with type overloaded calls. The crux of the matter is that because GlobalISel’s LowLevelTypes only carry size and vector layout information, and not any information about whether a type is integer or fp, we lose information during IR translation of type overloaded intrinsics.
>
> I’m pretty strongly opposed to #2. I think the more relaxed type system is one of the advantages over Se...
2017 Apr 06
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...Arch64 Linux.
>
> I saw one assertion failure in GlobalISel, see
> http://bugs.llvm.org/show_bug.cgi?id=32471. This is in a program compiled at
> -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for
> that program). The root cause of the failure seems to be due to LowLevelType
> not supporting vectors of pointers. I think this demonstrates that for
> correctness, we should be trying to test more than -O0, or even more than
> just LLVM-IR produced by clang, as other front-ends could run into this even
> at -O0.
>
> Due to this assertion failure and the i...
2017 Apr 26
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...sertion failure in GlobalISel, see http://bugs.llvm.org/show_bug.cgi?id=32471 <http://bugs.llvm.org/show_bug.cgi?id=32471>. This is in a program compiled at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for that program). The root cause of the failure seems to be due to LowLevelType not supporting vectors of pointers. I think this demonstrates that for correctness, we should be trying to test more than -O0, or even more than just LLVM-IR produced by clang, as other front-ends could run into this even at -O0.
>>
>> Due to this assertion failure and the infrastructu...
2017 Apr 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...sertion failure in GlobalISel, see http://bugs.llvm.org/show_bug.cgi?id=32471 <http://bugs.llvm.org/show_bug.cgi?id=32471>. This is in a program compiled at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for that program). The root cause of the failure seems to be due to LowLevelType not supporting vectors of pointers. I think this demonstrates that for correctness, we should be trying to test more than -O0, or even more than just LLVM-IR produced by clang, as other front-ends could run into this even at -O0.
>>>>
>>>> Due to this assertion failure and...
2017 Mar 29
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi,
GlobalISel, the SelectionDAG replacement, has come a long way since initially discussed on the mailing list and its last discussion at the EuroLLVM BoF (https://etherpad.net/p/GlobalISel <https://etherpad.net/p/GlobalISel>).
We believe we are close to the point of enabling it by default on AArch64 at O0. We now would like to enlist your help to get there.
*** Quick Status ***
On iOS
2017 May 09
4
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...running on Cortex-A57 AArch64 Linux.
I saw one assertion failure in GlobalISel, see http://bugs.llvm.org/show_bug.cgi?id=32471. This is in a program compiled at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for that program). The root cause of the failure seems to be due to LowLevelType not supporting vectors of pointers. I think this demonstrates that for correctness, we should be trying to test more than -O0, or even more than just LLVM-IR produced by clang, as other front-ends could run into this even at -O0.
Due to this assertion failure and the infrastructure I used, the num...
2017 May 09
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...4 Linux.
>
> I saw one assertion failure in GlobalISel, see
> http://bugs.llvm.org/show_bug.cgi?id=32471. This is in a program compiled
> at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for
> that program). The root cause of the failure seems to be due to
> LowLevelType not supporting vectors of pointers. I think this demonstrates
> that for correctness, we should be trying to test more than -O0, or even
> more than just LLVM-IR produced by clang, as other front-ends could run
> into this even at -O0.
>
> Due to this assertion failure and the infras...
2017 May 10
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...sertion failure in GlobalISel, see http://bugs.llvm.org/show_bug.cgi?id=32471 <http://bugs.llvm.org/show_bug.cgi?id=32471>. This is in a program compiled at -O2 (my out-dated test-suite still overrides -O0 and instead uses -O for that program). The root cause of the failure seems to be due to LowLevelType not supporting vectors of pointers. I think this demonstrates that for correctness, we should be trying to test more than -O0, or even more than just LLVM-IR produced by clang, as other front-ends could run into this even at -O0.
>>>>>>>>
>>>>>>>> Du...
2019 May 24
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ave been added to represent the same concepts
> at the SelectionDAG level, while splatvector maps onto the existing
> AArch64ISD::DUP.
>
> GlobalISel
> ----------
>
> Since GlobalISel was enabled by default on AArch64, it was necessary to add
> scalable vector support to the LowLevelType implementation. A single bit was
> added to the raw_data representation for vectors and vectors of pointers.
>
> In addition, types that only exist in destination patterns are planted in
> the enumeration of available types for generated code. While this may not be
> necessary in fut...
2018 Jul 30
5
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...e been added to represent the same concepts
> at the SelectionDAG level, while splatvector maps onto the existing
> AArch64ISD::DUP.
>
> GlobalISel
> ----------
>
> Since GlobalISel was enabled by default on AArch64, it was necessary to add
> scalable vector support to the LowLevelType implementation. A single bit was
> added to the raw_data representation for vectors and vectors of pointers.
>
> In addition, types that only exist in destination patterns are planted in
> the enumeration of available types for generated code. While this may not be
> necessary in fu...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...4 backend.
Two new AArch64ISD nodes have been added to represent the same concepts
at the SelectionDAG level, while splatvector maps onto the existing
AArch64ISD::DUP.
GlobalISel
----------
Since GlobalISel was enabled by default on AArch64, it was necessary to add
scalable vector support to the LowLevelType implementation. A single bit was
added to the raw_data representation for vectors and vectors of pointers.
In addition, types that only exist in destination patterns are planted in
the enumeration of available types for generated code. While this may not be
necessary in future, generating an all-t...
2019 May 24
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...4 backend.
Two new AArch64ISD nodes have been added to represent the same concepts
at the SelectionDAG level, while splatvector maps onto the existing
AArch64ISD::DUP.
GlobalISel
----------
Since GlobalISel was enabled by default on AArch64, it was necessary to add
scalable vector support to the LowLevelType implementation. A single bit was
added to the raw_data representation for vectors and vectors of pointers.
In addition, types that only exist in destination patterns are planted in
the enumeration of available types for generated code. While this may not be
necessary in future, generating an all-t...
2019 May 27
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...4 backend.
Two new AArch64ISD nodes have been added to represent the same concepts
at the SelectionDAG level, while splatvector maps onto the existing
AArch64ISD::DUP.
GlobalISel
----------
Since GlobalISel was enabled by default on AArch64, it was necessary to add
scalable vector support to the LowLevelType implementation. A single bit was
added to the raw_data representation for vectors and vectors of pointers.
In addition, types that only exist in destination patterns are planted in
the enumeration of available types for generated code. While this may not be
necessary in future, generating an all-t...
2019 Jun 03
2
[EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ave been added to represent the same concepts
> at the SelectionDAG level, while splatvector maps onto the existing
> AArch64ISD::DUP.
>
> GlobalISel
> ----------
>
> Since GlobalISel was enabled by default on AArch64, it was necessary to add
> scalable vector support to the LowLevelType implementation. A single bit was
> added to the raw_data representation for vectors and vectors of pointers.
>
> In addition, types that only exist in destination patterns are planted in
> the enumeration of available types for generated code. While this may not be
> necessary in fut...
2018 Jul 30
7
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...evel, while splatvector maps onto the existing
> > AArch64ISD::DUP.
> >
> > GlobalISel
> > ----------
> >
> > Since GlobalISel was enabled by default on AArch64, it was
> necessary to add
> > scalable vector support to the LowLevelType implementation. A
> single bit was
> > added to the raw_data representation for vectors and vectors of
> pointers.
> >
> > In addition, types that only exist in destination patterns are
> planted in
> > the enumeration of available types...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ave been added to represent the same concepts
> at the SelectionDAG level, while splatvector maps onto the existing
> AArch64ISD::DUP.
>
> GlobalISel
> ----------
>
> Since GlobalISel was enabled by default on AArch64, it was necessary to add
> scalable vector support to the LowLevelType implementation. A single bit was
> added to the raw_data representation for vectors and vectors of pointers.
>
> In addition, types that only exist in destination patterns are planted in
> the enumeration of available types for generated code. While this may not be
> necessary in fut...