search for: loweradd

...I also marked i1 as a legal type, but it caused a lot of problems. Now I pretend that the CC register can hold an i32. It just happens to always hold the values 0 and 1. The i1 logical operations are rarely needed, and they can be custom inserted when necessary, see BlackfinTargetLowering::LowerADDE(). I don't think you have to write custom lowering code to get the behaviour you want. Have you tried this: setOperationAction(ISD::OR, MVT::i1, Promote); If you can get your target to work with a legal i1 type, it would be great. The Blackfin target could use that as well. > Wh...

...rgetLowering::MxmTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { [...] setOperationAction(ISD::ADD, MVT::i32, Custom); [...] } //check for immediate adds with constant values -256 < x < 0 and transform them //to sub SDValue MxmTargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); if(ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) { int val = CN->getSExtValue(); if(val < 0 && val > -256) {...

Hi all, i'm writing an back-end for a new research processor architecture and have problems with the DAG Combiner. The processor architecture supports i1 and i32 registers. 1-bit registers are mainly used as comparison result but basic operations like OR are not possible between i1 registers. So I wrote custom lowering for i1 OR operations and replaced it by (trunc (or (aext x), (aext

...to an immediate or a value loaded from memory. There is no instruction that adds A to another register. I had thought LLVM would allocate a stack object for the second operand, but it didn't, and LLVM threw an ISel matching error. I currently solve this with a custom ADD lowering function, see LowerADD in M6502ISelLowering.cpp. Question: Is custom lowering ideal for this situation? Or, is there another way to coax LLVM into recognizing ADD? The problem I'm stuck on is folding memory operands. In the test file above, in @testSum, switch %a, %b to %b, %a. llc will assert in Register Spilling:...

...a legal type, but it caused > a lot of problems. Now I pretend that the CC register can hold an i32. > It just happens to always hold the values 0 and 1. The i1 logical > operations are rarely needed, and they can be custom inserted when > necessary, see BlackfinTargetLowering::LowerADDE(). I had also a lot of problems to get the i1 operations working. E.g. I had to override the getSetCCResultType to get is working and for ADDE/ADDC the i1 target registers are hardcoded. I'm writing the back-end to research the influence of several ISA characteristics on the processor perfor...