search for: loweradde

...I also marked i1 as a legal type, but it caused a lot of problems. Now I pretend that the CC register can hold an i32. It just happens to always hold the values 0 and 1. The i1 logical operations are rarely needed, and they can be custom inserted when necessary, see BlackfinTargetLowering::LowerADDE(). I don't think you have to write custom lowering code to get the behaviour you want. Have you tried this: setOperationAction(ISD::OR, MVT::i1, Promote); If you can get your target to work with a legal i1 type, it would be great. The Blackfin target could use that as well. > Wha...

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

Hi all, i'm writing an back-end for a new research processor architecture and have problems with the DAG Combiner. The processor architecture supports i1 and i32 registers. 1-bit registers are mainly used as comparison result but basic operations like OR are not possible between i1 registers. So I wrote custom lowering for i1 OR operations and replaced it by (trunc (or (aext x), (aext

Greetings, LLVM devs, For the past few weeks, I have been putting together a 6502 backend for LLVM. The 6502 and its derivatives, of course, have powered countless microcomputers, game consoles and arcade machines over the past 40 years. The backend is just an experimental hobby project right now. The code is available here: <https://github.com/beholdnec/llvm-m6502>. This branch introduces

...a legal type, but it caused > a lot of problems. Now I pretend that the CC register can hold an i32. > It just happens to always hold the values 0 and 1. The i1 logical > operations are rarely needed, and they can be custom inserted when > necessary, see BlackfinTargetLowering::LowerADDE(). I had also a lot of problems to get the i1 operations working. E.g. I had to override the getSetCCResultType to get is working and for ADDE/ADDC the i1 target registers are hardcoded. I'm writing the back-end to research the influence of several ISA characteristics on the processor perform...