Displaying 7 results from an estimated 7 matches for "loadi64".
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loadf64
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...a load with GRP:
> def: Pat<(load (addr_use_grp tglobaladdr:$addr)),
> (load (movimm tglobaladdr:$addr), GRP)>;
>
I'm not entirely sure what to replace 'load' with in the patterns above.
I notice that we have these defm's in our XSTGInstrInfo.td file:
defm LOADI64 : LoadOp< 0b1001010, "load", OpInfo_I64, II_LOAD1 >;
defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >;
defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >;
defm LOADF32 : LoadOp< 0b1001010, "load", OpInfo_F32,...
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote:
>
>> I've got this PseudoOp defined:
>>
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
>> def XSTGRELADDR :
2007 Dec 12
2
[LLVMdev] Bogus X86-64 Patterns
...erns in X86InstrX86-64.td are wrong. Specifically:
def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[(set VR128:$dst,
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128:
$src),
"mov{d|q}\t{$src, $dst|$dst, $src}",
[(store (i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0...
2016 Jun 28
2
Instruction selection problem with type i64 - mistaken as v8i64?
...ody
ldd REGVEC0, -128(r10)
ldd r0, -48(r10)
I am surprised that the BPF scalar instructions ldd and std use vector register
REGVEC0, which have type v8i64.
For example, the TableGen definition of the LOAD instruction taken from
BPFInstrInfo.td is:
class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
: LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
So I am surprised that the instruction selector finds as match for operand i64:$dst
the vector register REGVEC0, which has type v8i64 as defined...
2007 Dec 13
0
[LLVMdev] Bogus X86-64 Patterns
...rong. Specifically:
>
> def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins
> i64mem:$src),
> "mov{d|q}\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> (v2i64 (scalar_to_vector (loadi64 addr:
> $src))))]>;
>
> def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:
> $dst, VR128:
> $src),
> "mov{d|q}\t{$src, $dst|$dst, $src}",
> [(store (i64 (vector_extract (v2i64 VR128:
> $src),
&...
2016 Jun 29
0
Instruction selection problem with type i64 - mistaken as v8i64?
...)
> ldd r0, -48(r10)
>
> I am surprised that the BPF scalar instructions ldd and std use vector
> register
> REGVEC0, which have type v8i64.
> For example, the TableGen definition of the LOAD instruction taken from
> BPFInstrInfo.td is:
> class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
> : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
>
> So I am surprised that the instruction selector finds as match for operand
> i64:$dst
> the vector register REGVEC0, which ha...
2011 Sep 30
2
[LLVMdev] LLVM backends instruction selection
I am new to the LLVM backends, I am wondering how instruction selection is
done in LLVM backends, I looked at the .td files in Target/X86, they all
seem to be small and do not deal with common X86 instructions, i.e. mov,
push, pop, etc.
Thanks
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