search for: loadf64

I tried to add an 'OptForSize' requirement to a pattern in X86InstrSSE.td, but it appears to be ignored. However, the condition was detected when specified as a predicate. So this doesn't work: def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm addr: $src)>, *Requires<[OptForSize**]>*; But this does: * let Predicates = [OptForSize] in* { def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm addr :$src)>; } I see both forms used on some patterns like this: *...

...> I tried to add an 'OptForSize' requirement to a pattern in X86InstrSSE.td, > > but it appears to be ignored. However, the condition was detected when > > specified as a predicate. > > > > So this doesn't work: > > def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm > addr: > > $src)>, > > *Requires<[OptForSize**]>*; > > > > But this does: > > * let Predicates = [OptForSize] in* { > > def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm > addr...

...to clean up > nodes that become dead during selection, but my guess is that > it's missing some cases. Ok, as far as I can tell, here's what's happening. I have the following pattern: let AddedComplexity = 40 in { def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr: $src1))), (v2f64 (scalar_to_vector (loadf64 addr: $src2))), SHUFP_shuffle_mask:$sm)), (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)), (v2f64 (MOVSD2PDrm addr:$src2)), S...

...// rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (bitconvert > (v2f64 (scalar_to_vector > (loadf64 addr:$src2))))))))], > // rr Pat > [], > // rm Pat > [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), > (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], > [(INTDSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2)...

...dead during selection, but my guess is that >> it's missing some cases. > > Ok, as far as I can tell, here's what's happening. > > I have the following pattern: > > let AddedComplexity = 40 in { > def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 > addr: > $src1))), > (v2f64 (scalar_to_vector (loadf64 > addr: > $src2))), > SHUFP_shuffle_mask:$sm)), > (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)), > (v2f64 (MOVSD2PDrm...

On Fri, October 3, 2008 9:10 am, David Greene wrote: > On Thursday 02 October 2008 19:32, Dan Gohman wrote: > >> Looking at your dump() output above, it looks like the pre-selection >> loads have multiple uses, so even though you've managed to match a >> larger pattern that incorporates them, they still need to exist to >> satisfy some other users. > > Yes,

...[(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))))], // rr Pat [], // rm Pat [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], [(INTDSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), (MNEMON...

On Thursday 02 October 2008 19:32, Dan Gohman wrote: > Looking at your dump() output above, it looks like the pre-selection > loads have multiple uses, so even though you've managed to match a > larger pattern that incorporates them, they still need to exist to > satisfy some other users. Yes, I looked at that too. It looks like these other uses end up being chains to

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

...[(set DSTREGCLASS:$dst, >> (DSTTYPE (movlhps SRCREGCLASS:$src1, >> (DSTTYPE (bitconvert >> (v2f64 (scalar_to_vector >> (loadf64 addr:$src2))))))))], >> // rr Pat >> [], >> // rm Pat >> [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), >> (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], >> [(INTDSTTYPE (movlhps SRCREGCLASS:...

...y I remove SSEPackedSingle/SSEPackedDouble domain from it? defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32, "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG; defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX, VEX_LIG; let Pattern = []<dag> in { defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load, "comiss...

On Thursday 02 October 2008 11:37, David Greene wrote: > I'll try ot write a small example and send it in a bit. Ok, here's what I'm trying to do: let AddedComplexity = 40 in { def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr: $src1))), (v2f64 (scalar_to_vector (loadf64 addr: $src2))), SHUFP_shuffle_mask:$sm)), (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)), (v2f64 (MOVSD2PDrm addr:$src2)), SHUFP_sh...

Ok, this is really complicated. I need some TableGen experts to help here. I need a little help doing a final bit of tblgen hacking. I've hacked tblgen to handle patterns like this: let AddedComplexity = 40 in { def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))), (v2f64 (scalar_to_vector (loadf64 addr:$src2))), SHUFP_shuffle_mask:$sm), (SHUFPDrri (MOVSD2PDrm addr:$src1), (MOVSD2PDrm addr:$src2), SHUFP_shuffle_mask:$sm)>, Requires<[...

I'm debugging some X86 patterns and I want to understand the debug dumps from isel better. Here's some example output: 0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext i32> alignment=4 srcLineNum= 10 0x3922c50: <multiple use> 0x391bc40: <multiple use> 0x3856ab0: <multiple use> 0x3914520: i64 =

...(load (movimm tglobaladdr:$addr), GRP)>; > I'm not entirely sure what to replace 'load' with in the patterns above. I notice that we have these defm's in our XSTGInstrInfo.td file: defm LOADI64 : LoadOp< 0b1001010, "load", OpInfo_I64, II_LOAD1 >; defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >; defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >; defm LOADF32 : LoadOp< 0b1001010, "load", OpInfo_F32, II_LOAD1 >; defm LOADI16 : LoadOp< 0b1001010, "load", OpInfo_I16,...

...et DSTREGCLASS:$dst, >>> (DSTTYPE (movlhps SRCREGCLASS:$src1, >>> (DSTTYPE (bitconvert >>> (v2f64 (scalar_to_vector >>> (loadf64 addr:$src2))))))))], >>> // rr Pat >>> [], >>> // rm Pat >>> [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), >>> (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], >>> [(INTDSTTYPE (mo...

.../ rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (bitconvert > (v2f64 (scalar_to_vector > (loadf64 addr:$src2))))))))], > // rr Pat > [], > // rm Pat > [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), > (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], > [(INTDSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:...

On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote: > >> I've got this PseudoOp defined: >> >> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>; >> def XSTGRELADDR :

...[(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))))], // rr Pat [], // rm Pat [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], [(INTDSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), (MNEMON...

...$dst, >>>>                (DSTTYPE (movlhps SRCREGCLASS:$src1, >>>>                                (DSTTYPE (bitconvert >>>>                                            (v2f64 (scalar_to_vector >>>>                                                      (loadf64 addr:$src2))))))))], >>>>          // rr Pat >>>>          [], >>>>          // rm Pat >>>>          [[(DSTTYPE (movlhps SRCREGCLASS:$src1, (load addr:$src2))), >>>>            (MNEMONIC SRCREGCLASS:$src1, addr:$src2)], >>>>  ...