search for: lmsw

The lmsw instruction can be used to set CR0_PE, but can never clear it, once set. Currently, as far as I can see, there is no provision to keep lmsw from clearing CR0_PE, either in the vmx code or in x86_emulate code (which is used by SVM to emulate lmsw). This patch fixes this issue. Signed-off-by: Trolle...

Hi, When I map directory using samba o nour Windows 2000, I have to type in the IP address of the samba server or the complete domain name; i.e, host.lmsw.lmco.com. I can't just type in the hostname; i.e. host. Your help is very much apreciated. Thanks Aissa Char Lockheed Martin Aero

...BASE,sizeof(unsigned long),1,fp); + fwrite(&b,sizeof(char),1,fp); + fwrite(&CR3,sizeof(unsigned long),1,fp); + fwrite(&a,sizeof(char),1,fp); + + fclose(fp); + exit_qualification = __vmread(EXIT_QUALIFICATION); inst_len = __get_instruction_length(); /* Safe: MOV Cn, LMSW, CLTS */ if ( vmx_cr_access(exit_qualification, regs) ) ----------------------------------------------------------------------------------------------------- but when I compiled the xen,the error occured: vmx.c:53:19: 错误：stdio.h：No such file or directory vmx.c:54:20: 错误：stdlib.h：No such...

Hi all, Does anyone have thoughts on extending v->arch.hvm_vcpu.single_step to support pre-MTF systems, in a way that would mimic the MTF? So far I''m emulating PUSHF/POPF to hide the hypervisor''s trap flag, and eventually I''ll multiplex it down to the guest, but I''m having issues. Right now, I''m enabling X86_EFLAGS_TF in vmx_intr_assist, just like

...ects page, found some interesting projects but still have some questions about them: "Add support for 16-bit x86 assembly and real mode to the assembler and disassembler, for use by BIOS code. This includes both 16-bit instruction encodings as well as privileged instructions (lgdt, lldt, ltr, lmsw, clts, invd, invlpg, wbinvd, hlt, rdmsr, wrmsr, rdpmc, rdtsc) and the control and debug registers." Correct me if I'm mistaken, but isn't this already implemented in llvm mc? I haven't searched for every instruction part of these architectures but I was able find to some of the pr...

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page

...rampoline is under 1M, and shift its start into + # %fs to reference symbols in that area + movl $BOOT_TRAMPOLINE, %eax + shrl $4, %eax + movl %eax, %fs + lidt %fs:bootsym(idt_48) + lgdt %fs:bootsym(gdt_48) + + movw $1, %ax + lmsw %ax # Turn on CR0.PE + jmp 1f +1: + ljmpl $BOOT_CS32, $bootsym_phys(wakeup_32) + +/* This code uses an extended set of video mode numbers. These include: + * Aliases for standard modes + * NORMAL_VGA (-1) + * EXTENDED_VGA (-2) + * ASK_VGA (-3) + *...

...s, that + is, inline implementations of the native instructions, which are not + rewritten by the hypervisor. Some of these calls are performance critical + during context switch paths, and some are not, but they are all included + for completeness, with the exceptions of the obsoleted LMSW and SMSW + instructions. + + VMI_WRMSR + + VMICALL void VMI_WRMSR(VMI_UINT64 val, VMI_UINT32 reg); + + Write to a model specific register. This functions identically to the + hardware WRMSR instruction. Note that a hypervisor may not implement + the full set of MSRs...

...s, that + is, inline implementations of the native instructions, which are not + rewritten by the hypervisor. Some of these calls are performance critical + during context switch paths, and some are not, but they are all included + for completeness, with the exceptions of the obsoleted LMSW and SMSW + instructions. + + VMI_WRMSR + + VMICALL void VMI_WRMSR(VMI_UINT64 val, VMI_UINT32 reg); + + Write to a model specific register. This functions identically to the + hardware WRMSR instruction. Note that a hypervisor may not implement + the full set of MSRs...

...; for samba@lists.samba.org; Mon, 25 Jun 2001 17:45:58 -0600 (MDT) Received: from emss08m01.ems.lmco.com ([144.197.176.1]) by lmco.com (PMDF V5.2-33 #38887) with ESMTP id <0GFI009IAFCH5M@lmco.com> for samba@lists.samba.org; Mon, 25 Jun 2001 17:45:53 -0600 (MDT) Received: from skunkworks.lmsw.lmco.com ([144.197.7.2]) by emss08m01.ems.lmco.com with SMTP (Microsoft Exchange Internet Mail Service Version 5.5.2653.13) id N3ZXL56V; Mon, 25 Jun 2001 16:46:59 -0700 Received: from lmco.com ([144.197.174.175]) by skunkworks.lmsw.lmco.com (post.office MTA v2.0 0813 ID# 0-11530) with ESMTP...