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...concrete proposal for LLVM representations of atomic operations and > synchronization constructs. These aim to provide the minimal > functionality in the IR for representing the hardware constructs that > threading libraries and parallel programming rely on. > > http://chandlerc.net/llvm_atomics.html > > While I am no expert on the various architectures, I've done my best > at providing base-line implementations for each instruction. I am sure > these will need tweaking and fixing, but should provide a very good > starting point for the targets. > > Comments are...

...k, I have put together a concrete proposal for LLVM representations of atomic operations and synchronization constructs. These aim to provide the minimal functionality in the IR for representing the hardware constructs that threading libraries and parallel programming rely on. http://chandlerc.net/llvm_atomics.html While I am no expert on the various architectures, I've done my best at providing base-line implementations for each instruction. I am sure these will need tweaking and fixing, but should provide a very good starting point for the targets. Comments are more than welcome, especially su...

...VM representations of atomic operations and > > synchronization constructs. These aim to provide the minimal > > functionality in the IR for representing the hardware constructs that > > threading libraries and parallel programming rely on. > > > > http://chandlerc.net/llvm_atomics.html > > > > While I am no expert on the various architectures, I've done my best > > at providing base-line implementations for each instruction. I am sure > > these will need tweaking and fixing, but should provide a very good > > starting point for the target...

...SA, so removing that aspect of the atomic primitives makes the *LLVM* representation easier to understand. > And having another version that returns > just a bool might be better in some cases ( 1. does CAS return the value on > all architectures? Check the page (http://chandlerc.net/llvm_atomics.html -- the implementation info is still current, even though the docs are not) for how this gets implemented. As Andrew has already pointed out, on x86, the LLVM behavior maps to the underlying architecture. Other architectures which might avoid a compare can easily do so by pattern matchi...

...mic operations and > > > synchronization constructs. These aim to provide the minimal > > > functionality in the IR for representing the hardware constructs that > > > threading libraries and parallel programming rely on. > > > > > > http://chandlerc.net/llvm_atomics.html > > > > > > While I am no expert on the various architectures, I've done my best > > > at providing base-line implementations for each instruction. I am sure > > > these will need tweaking and fixing, but should provide a very good > > > star...

...concrete proposal for LLVM representations of atomic operations and > synchronization constructs. These aim to provide the minimal > functionality in the IR for representing the hardware constructs that > threading libraries and parallel programming rely on. > > http://chandlerc.net/llvm_atomics.html > > While I am no expert on the various architectures, I've done my best > at providing base-line implementations for each instruction. I am sure > these will need tweaking and fixing, but should provide a very good > starting point for the targets. > > Comments are...

On Wednesday 20 February 2008 01:51, Andrew Lenharth wrote: > Anyone have an idea? The patch as it stands is attached below. X86 > is a pseudo instruction because the necessary ones and prefixes aren't > in the code gen yet, but I would imagine they will be (so ignore that > ugliness). The true ugliness can be seen in the alpha impl which open > codes it, including a couple

I was working on compare and swap and ran into the following problem. Several architectures implement this with a load locked, store conditional sequence. This is good, for those archs I can write generic code to legalize a compare and swap (and most other atomic ops) to load locked store conditional sequences (then the arch only had to give the instr for ldl, stc to support all atomic ops (this

...concrete proposal for LLVM representations of atomic operations and > synchronization constructs. These aim to provide the minimal > functionality in the IR for representing the hardware constructs that > threading libraries and parallel programming rely on. > > http://chandlerc.net/llvm_atomics.html > > While I am no expert on the various architectures, I've done my best > at providing base-line implementations for each instruction. I am sure > these will need tweaking and fixing, but should provide a very good > starting point for the targets. > > Comments are...

Hello, This is the second major revision of the atomic proposal for LLVM. I will try and give a brief overview of the motivating changes, but a greater portion of the text has changed, along with some changes to the proposed additions. http://chandlerc.net/llvm_atomics.html - The proposal has been rewritten to better delineate the goals and purposes of LLVM, and these additions to LLVM. The why and to what purpose has been a source of confusion, and this is addressed directly. - The explanation of memory barriers and why the representation was chosen has been...