Displaying 9 results from an estimated 9 matches for "llsc".
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2016 Jan 10
48
[PATCH v3 00/41] arch: barrier cleanup + barriers for virt
...++++++-----------
arch/powerpc/include/asm/barrier.h | 33 ++++-------
arch/s390/include/asm/barrier.h | 23 ++++----
arch/sh/include/asm/barrier.h | 3 +-
arch/sh/include/asm/cmpxchg-grb.h | 22 ++++++++
arch/sh/include/asm/cmpxchg-irq.h | 11 ++++
arch/sh/include/asm/cmpxchg-llsc.h | 25 +--------
arch/sh/include/asm/cmpxchg-xchg.h | 51 +++++++++++++++++
arch/sh/include/asm/cmpxchg.h | 3 +
arch/sparc/include/asm/barrier_32.h | 1 -
arch/sparc/include/asm/barrier_64.h | 29 ++--------
arch/sparc/include/asm/processor.h | 3 -
arch/tile/include/asm/barrier...
2016 Jan 10
48
[PATCH v3 00/41] arch: barrier cleanup + barriers for virt
...++++++-----------
arch/powerpc/include/asm/barrier.h | 33 ++++-------
arch/s390/include/asm/barrier.h | 23 ++++----
arch/sh/include/asm/barrier.h | 3 +-
arch/sh/include/asm/cmpxchg-grb.h | 22 ++++++++
arch/sh/include/asm/cmpxchg-irq.h | 11 ++++
arch/sh/include/asm/cmpxchg-llsc.h | 25 +--------
arch/sh/include/asm/cmpxchg-xchg.h | 51 +++++++++++++++++
arch/sh/include/asm/cmpxchg.h | 3 +
arch/sparc/include/asm/barrier_32.h | 1 -
arch/sparc/include/asm/barrier_64.h | 29 ++--------
arch/sparc/include/asm/processor.h | 3 -
arch/tile/include/asm/barrier...
2016 Jan 13
3
[PULL] virtio: barrier rework+fixes
...-----
arch/powerpc/include/asm/barrier.h | 33 ++++------
arch/s390/include/asm/barrier.h | 23 ++++---
arch/sh/include/asm/barrier.h | 3 +-
arch/sh/include/asm/cmpxchg-grb.h | 22 +++++++
arch/sh/include/asm/cmpxchg-irq.h | 11 ++++
arch/sh/include/asm/cmpxchg-llsc.h | 25 +-------
arch/sh/include/asm/cmpxchg-xchg.h | 51 ++++++++++++++++
arch/sh/include/asm/cmpxchg.h | 3 +
arch/sparc/include/asm/barrier_32.h | 1 -
arch/sparc/include/asm/barrier_64.h | 29 ++-------
arch/sparc/include/asm/processor.h | 3 -
arch/tile/incl...
2016 Jan 13
3
[PULL] virtio: barrier rework+fixes
...-----
arch/powerpc/include/asm/barrier.h | 33 ++++------
arch/s390/include/asm/barrier.h | 23 ++++---
arch/sh/include/asm/barrier.h | 3 +-
arch/sh/include/asm/cmpxchg-grb.h | 22 +++++++
arch/sh/include/asm/cmpxchg-irq.h | 11 ++++
arch/sh/include/asm/cmpxchg-llsc.h | 25 +-------
arch/sh/include/asm/cmpxchg-xchg.h | 51 ++++++++++++++++
arch/sh/include/asm/cmpxchg.h | 3 +
arch/sparc/include/asm/barrier_32.h | 1 -
arch/sparc/include/asm/barrier_64.h | 29 ++-------
arch/sparc/include/asm/processor.h | 3 -
arch/tile/incl...
2008 Jul 08
0
[LLVMdev] Trying to compile llvm-gcc to mips
>
> The problem is with libgcc2, which contains libcalls needed to support
> some operations
> your processor cant directly do.
>
Yes, I mix up libgcc2 with libcpp... I have advanced a little, commenting
out the fp functions. Now, it stucks at unwind-dw2.c. MipsISelLowering.cpp
gives the error: Unsupported calling convention.
By the way, I understand that these functions are
2018 Jun 13
12
RFC: Atomic LL/SC loops in LLVM revisited
# RFC: Atomic LL/SC loops in LLVM revisited
## Summary
This proposal gives a brief overview of the challenges of lowering to LL/SC
loops and details the approach I am taking for RISC-V. Beyond getting feedback
on that work, my intention is to find consensus on moving other backends
towards a similar approach and sharing common code where feasible. Scroll down
to 'Questions' for a summary
2008 Jul 07
2
[LLVMdev] Trying to compile llvm-gcc to mips
Hi Julio,
On Mon, Jul 7, 2008 at 6:53 AM, Julio <julio.martin.hidalgo at gmail.com> wrote:
> And one last thing, the problem seems to be related to libcpp. Using only C
> frontend will work?
The problem is with libgcc2, which contains libcalls needed to support
some operations
your processor cant directly do.
>> Actually, I don't need fp, there is any way to disable?
2016 Jan 18
0
virtio pull for 4.5 (was Re: [PULL] virtio: barrier rework+fixes)
...de/asm/barrier.h | 33 ++++------
> arch/s390/include/asm/barrier.h | 23 ++++---
> arch/sh/include/asm/barrier.h | 3 +-
> arch/sh/include/asm/cmpxchg-grb.h | 22 +++++++
> arch/sh/include/asm/cmpxchg-irq.h | 11 ++++
> arch/sh/include/asm/cmpxchg-llsc.h | 25 +-------
> arch/sh/include/asm/cmpxchg-xchg.h | 51 ++++++++++++++++
> arch/sh/include/asm/cmpxchg.h | 3 +
> arch/sparc/include/asm/barrier_32.h | 1 -
> arch/sparc/include/asm/barrier_64.h | 29 ++-------
> arch/sparc/include/asm/processor.h...
2007 Jul 09
1
[LLVMdev] Proposal for atomic and synchronization instructions
> > > "While the processor may spin and attempt the atomic operation more than
> > > once before it is successful, research indicates this is extremely
> > > uncommon." I don't understand this sentence, what do you mean?
> >
> > I'm not sure I can pinpoint the paper from which the statement is based,
> > but I seem to recall something