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Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend on LiveVariables which require the machine function to be in SSA form. However, in this case, the modified machine function(including newly inserted MBB) is not SSA form any more. So, how to update LiveInterva...

Andy, Jacob, I have ported Hexagon MI scheduler to use the new scheduler infrastructure, but one of my tests triggers an assert in LiveInterval update. On the surface it does not make much sense to me, so I wonder if this is something you readily recognize, before I try to prop it open... The assert is: lib/CodeGen/LiveInterval.cpp:266: llvm::LiveRange* llvm::LiveInterval::addRangeFrom(llvm::LiveRange, llvm::LiveRange*): Assertion `B-&g...

...Hi, I insert a new machine basic block(MBB) before Greedy Register Allocation, after Simple Register Coalescing. But I encounter a fatal error "regalloc = ... not currently supported with -O0". I use command line with opt level O2, not O0. The probable reason of this error is that no LiveInterval information for newly MBB which is used by Register Allocation. And, LiveIntervals depend on LiveVariables which require the machine function to be in SSA form. However, in this case, the modified machine function(including newly inserted MBB) is not SSA form any more. So, how to update LiveInterva...

...can whittle it down. It's a pretty huge function. If it's a coalescing bug it's probably in my code since I'm not using the current default llvm coalescer. It may be that I'm updating dataflow information incorrectly. I'll check on that. > > If so, then isn't LiveInterval::Ranges and LiveInterval::VNInfoList > > redundant? > > What's in VNInfoList that's not in the valno member of the Ranges > > elements, > > and vice-versa? > > I am not sure if I understand your question. Multiple liveranges can > be of the same val#. Each V...

...ycle with a redefined LiveRange::overlap-function. On a multiple-issue cycle, a register that gets killed > can be reused by another MI - these live ranges do not then overlap. Redefining overlap() won't work for that. There is other code assuming that overlap means overlap, for example the LiveIntervalUnion used by the new register allocators. For VLIW, you probably want to number your packets instead of individual instructions. We don't have any VLIW support, so nobody has thought about how best to do it. > Well, I would like to schedule the VLIW code after SimpleRegisterCoalescer, so t...

...er that gets killed can be reused by another MI - these live ranges do not then overlap. Well, I would like to schedule the VLIW code after SimpleRegisterCoalescer, so that I get more or less the final code to work with. As the instructions are rearrange, I suppose I must run the SlotIndexes and LiveIntervals again. LiveVariables should also be refreshed as a register might get killed with a different MI if two users change place, etc, I suppose. I would like to just rerun these passes, but you said below that LiveIntervals do not work after SSA form is abandoned. I wonder how you mean to update the...

Thanks Matthias I can also use the method intervalIsInOneMBB() from LiveIntervals class to relate a LiveInterval to a MachineBasicBlock, right? Em 04/09/2015 2:26 PM, "Matthias Braun" <mbraun at apple.com> escreveu: > There is no direct support for this, but you can use > LiveIntervalAnalysis::getMBBStartIndex()/getMBBEndIndex()/getMBBFromIndex() > to...

I though LiveVariables may be invalidated by LiveIntervals, but it's declared not: void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { AU.addPreserved<LiveVariables>(); AU.addRequired<LiveVariables>(); ... LiveInterval may coalesce virtual registers and remove identity moves instructions: bool LiveIntervals::runOnM...

On Jan 4, 2014, at 4:38 AM, Haishan <hndxvon at 163.com> wrote: > At 2014-01-04 06:11:38,"Jakob Stoklund Olesen" <stoklund at 2pi.dk> wrote: > > On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > >> He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all the intervals rerun LiveIntervals::computeVirtRegs after all the CFG transforms are complete? > > Yes, I should think so. > > /jakob > > > Thank you very much for your talk. > I think I...

...solve.f, line 23, in loop at depth 1, > bb16,0x83a2c70>, > %EFLAGS<imp-use,kill> > > Here we have the curious case of %reg1055 being defined and then > immediately > killed. It's a dead assignment. Why it wasn't removed I don't > know, but the > LiveInterval looks like this: > > %reg1055,0 = [308,348:0 [0]) 0 at 326-(326 326) > > The valno->def is 326, which is what I would expect given the > instruction > numbering above. > > So why does the live range extend throughout the entire basic block? > > %reg1055 doesn'...

Hi, I'm working on the implementation of Extended Linear Scan register allocator as described by Sarkar & Bodik. One of the interesting features of their algorithm is the possibility to allocate different physical registers to different live-ranges of the same LiveInterval. Of course, it may require some glue code to be inserted in cases, where different physical regs were assigned to live-ranges (of the same LiveInterval ) connected by a control-flow edge. I have almost implemented the algorithm for register assignments on a live-range basis. But now I need to rewr...

On Jan 3, 2014, at 1:52 PM, Andrew Trick <atrick at apple.com> wrote: > He really just wants to rerun LiveIntervals analysis, but LiveVariables is no longer available. Would it work just to clear all the intervals rerun LiveIntervals::computeVirtRegs after all the CFG transforms are complete? Yes, I should think so. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: <ht...

...llocator (-regalloc=pbqp), whereas LLVM uses linear scan by default (-regalloc=linscan). That's why you're not seeing it called. LLVM does not currently have an interference graph as such, because we do not have a graph coloring register allocator. You can get the same information from the LiveIntervals pass though. The LiveIntervals pass holds a set of LiveInterval objects, one for each register (both virtual and physical) that is live in the function. Each LiveInterval object describes the set of instructions for which its register is live. The LiveInterval::overlaps method will tell you whethe...

...ant to transform: ... %vreg1 = V_MOV_B32 1 %vreg2 = V_ADD_I32 %vreg1, %vreg0 ... into: %vreg1 = V_MOV_B32 1 ; <- Only delete this if it is dead %vreg2 = V_ADD_I32 1, %vreg0 For best results, I am trying to run this pass after the TwoAddressInstruction pass, which means I need to preserve the LiveIntervals analysis. My question is: How do I update the LiveIntervals to reflect the fact that V_ADD_I32 no longer uses %vreg0? Thanks, Tom

Hello to all LLVM Developers. Given a object from a LiveInterval class, is there any way to know if this Live Interval is part or is inside a loop? Att -- Natanael Ramos Membro do corpo discente de Ciência da Computação pelo Instituto Federal de Minas Gerais - Campus Formiga -------------- next part -------------- An HTML attachment was scrubbed... URL: <h...

...have a 'usual' pass, which can be used by the 'opt' tool, we can just pass the '-analyze' command line argument but what about the 'llc' compiler? As I can see, there is an implementation of the 'print(raw_ostream &OS, const Module*)' method in the 'LiveIntervals.cpp'. void LiveIntervals::print(raw_ostream &OS, const Module* ) const { OS << "********** INTERVALS **********\n"; // Dump the regunits. ... The method also is implemented in 'RegisterCoalescer.cpp' (in fact, this method just invokes one from LiveIntervals)...

...>>>> >>>> At 2014-01-01 04:36:21,"Andrew Trick" <atrick at apple.com> wrote: >>>> >>>> On Dec 31, 2013, at 3:52 AM, Haishan <hndxvon at 163.com> wrote: >>>> My update steps are shown following: >>>> LiveIntervals *LIS = &getAnalysis<LiveIntervals>(); >>>> 1. LIS->insertMBBInMaps(NewMBB) >>>> 2. LIS->InsertMachineInstrRangeInMaps(NewMBB->begin(), NewMBB->end()) >>>> 3. Due to some machine instructions of NewMBB copy from OldMBB, I have to...

...Hi, > > I'm working on the implementation of Extended Linear Scan register > allocator as described by Sarkar & Bodik. > One of the interesting features of their algorithm is the possibility > to allocate different physical registers to different live-ranges of > the same LiveInterval. Of course, it may require some glue code to be > inserted in cases, where different physical regs were assigned to > live-ranges (of the same LiveInterval ) connected by a control-flow > edge. > > I have almost implemented the algorithm for register assignments on a > live-range...

...%EFLAGS<imp-def> 344 JNS mbb<file solve.f, line 23, in loop at depth 1, bb16,0x83a2c70>, %EFLAGS<imp-use,kill> Here we have the curious case of %reg1055 being defined and then immediately killed. It's a dead assignment. Why it wasn't removed I don't know, but the LiveInterval looks like this: %reg1055,0 = [308,348:0 [0]) 0 at 326-(326 326) The valno->def is 326, which is what I would expect given the instruction numbering above. So why does the live range extend throughout the entire basic block? %reg1055 doesn't appear anywhere else in the program so it sho...

Toward a better register allocator, I'm attempting to understand the dataflow information available to the allocator. What's the difference between LiveInterval information and LiveVariable information? If a LiveInterval is based on a linear ordering of the machine instructions, isn't it rather conservative in nature? Let's say I have a typical diamond CFG: A / \ B C \ /...