search for: liveint

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2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...nalyze,Insert,Remove}Branch should be fixable. I don't think that the problem was with those functions. Adding support for BDNZ and friends in those functions just enabled other passes to start moving the blocks around, and that seems to have exposed problems of its own. For example, sometimes LiveIntervals asserts with: register: %CTR8 clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: void llvm::LiveInterval s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, llvm::MachineBasicBlock::iterator, llvm::SlotIndex, llvm::MachineOperand&, llvm::LiveInt erval&): A...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > For example, sometimes LiveIntervals asserts with: > register: > %CTR8 > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > void llvm::LiveInterval > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > llvm::MachineBasicBlock::iterator, llvm::SlotIndex, > llvm::MachineOperand&...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...veryone, I am working on a release based on the branch 3.1 version of code. Unfortunately it has enough differences that exact rev does not apply. I am hitting an assert in liveness update with seemingly trivial code (attached). /local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter valAnalysis.cpp:1078: void llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr*, llvm::SlotIndex): Assertion `validator.rangesOk() && "moveAllOperandsFrom broke liveness."' failed. The code being scheduled (function "push") is trivial: # Machine c...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Looking at VLIWPacketizerList::PacketizeMIs, it seems like the > instructions are first scheduled (via some external scheme?), and then > packetized 'in order'. Is that correct? Anshu? > In the PowerPC grouping scheme, resources are assigned on a group > basis (by the instruction dispatching
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Fri, 8 Jun 2012 08:49:32 -0700 Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: > > On Jun 7, 2012, at 10:54 PM, Hal Finkel wrote: > > > For example, sometimes LiveIntervals asserts with: > > register: > > %CTR8 > > clang: /llvm-trunk/lib/CodeGen/LiveIntervalAnalysis.cpp:446: > > void llvm::LiveInterval > > s::handlePhysicalRegisterDef(llvm::MachineBasicBlock*, > > llvm::MachineBasicBlock::iterator, llvm::SlotInd...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...on a release based on the branch 3.1 version of code. > Unfortunately it has enough differences that exact rev does not apply. > I am hitting an assert in liveness update with seemingly trivial code > (attached). > > /local/mnt/workspace/slarin/tools/llvm-mainline-merged/lib/CodeGen/LiveInter > valAnalysis.cpp:1078: void > llvm::LiveIntervals::HMEditor::moveAllRangesFrom(llvm::MachineInstr*, > llvm::SlotIndex): Assertion `validator.rangesOk() && "moveAllOperandsFrom > broke liveness."' failed. > > The code being scheduled (function "push&q...
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700 Andrew Trick <atrick at apple.com> wrote: > On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > I'm considering writing more-detailed itineraries for some PowerPC > > CPUs that use the 'traditional' instruction grouping scheme. In > > essence, this means that multiple instructions will stall
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the