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On Dec 12, 2011, at 2:51 PM, Tony Linthicum wrote: > On 12/12/2011 4:49 PM, Eric Christopher wrote: >> >> >> On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: >> >>> >>> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >>> >>>> On 12/12/2011 4:28 PM, Jakob Stoklund...

On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: > > On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: > >> On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >>> >>> >>> On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: >>> >>>> Hi folks, >>>> >>>> I just committed a new backend for the Hexagon processor....

I'm hitting this. Is there ETA for the fix? Evan On Dec 12, 2011, at 2:58 PM, Daniel Dunbar wrote: > > On Dec 12, 2011, at 2:51 PM, Tony Linthicum wrote: > >> On 12/12/2011 4:49 PM, Eric Christopher wrote: >>> >>> >>> On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: >>> >>>> >>>> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >>>> >>>>&g...

On 12/12/2011 4:49 PM, Eric Christopher wrote: > > On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: > >> >> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >> >>> On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >>>> >>>> On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: >>>> >>>>> Hi folks, >>>>> >>>>> I just committed a new backend for the Hexa...

...s, respectively). Most of the patches consist of, quite naturally, new files. I have looked for guidelines for submitting a new backend, but have not found anything. Is there anything of that nature? If not, my plan is to simply submit the two patches. Any other suggestions? Thanks. Tony Linthicum -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.

On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: > > On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: > >> Hi folks, >> >> I just committed a new backend for the Hexagon processor. After >> committing, I was able to successfully check out, build and test with >> the new changes. The x86_64 build on the buildbot is failing, >> however. Here's t...

On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: > On 12/12/2011 4:28 PM, Jakob Stoklund Olesen wrote: >> >> >> On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: >> >>> Hi folks, >>> >>> I just committed a new backend for the Hexagon processor. After committing, I was able to suc...

On Tue, Nov 1, 2011 at 11:44 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor.  We will actively maintain the port once it is accepted. > Hexagon is a VLIW core that is used principally in modem and low power > audio appl...

...an - ability to run newly produced binary on newly supported target? Can you please elaborate? Thanks. Sergei Larin -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Tuesday, November 01, 2011 1:58 PM To: Tony Linthicum Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Contributing new backend to LLVM On Tue, Nov 1, 2011 at 11:44 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hello all, > > We would like to contribute a new backend for Qualcomm's Hexagon > processor.  We will activel...

...clean? I'll try and find a real fix tomorrow. - Daniel On Dec 12, 2011, at 5:44 PM, Evan Cheng wrote: > I'm hitting this. Is there ETA for the fix? > > Evan > > On Dec 12, 2011, at 2:58 PM, Daniel Dunbar wrote: > >> >> On Dec 12, 2011, at 2:51 PM, Tony Linthicum wrote: >> >>> On 12/12/2011 4:49 PM, Eric Christopher wrote: >>>> >>>> >>>> On Dec 12, 2011, at 2:41 PM, Eric Christopher wrote: >>>> >>>>> >>>>> On Dec 12, 2011, at 2:36 PM, Tony Linthicum wrote: >...

On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: > Hi, > > On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>> Hi, >>> >>>> (4) llc -march=hexagon test.ll -o test.s >>>> >>>> '' is not a recognized processor for this target (ignoring processor) >>&...

On Dec 12, 2011, at 2:12 PM, Tony Linthicum wrote: > Hi folks, > > I just committed a new backend for the Hexagon processor. After committing, I was able to successfully check out, build and test with the new changes. The x86_64 build on the buildbot is failing, however. Here's the build error: > > llvm[2]: Linking D...

On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > Hey folks, > > We are having some difficulty with how we have been representing our > predicate registers, and wanted some advice from the list.  First, we > had been representing our predicate registers as 1 bit (i1).  The truth, > howeve...

Hi folks, I just committed a new backend for the Hexagon processor. After committing, I was able to successfully check out, build and test with the new changes. The x86_64 build on the buildbot is failing, however. Here's the build error: llvm[2]: Linking Debug+Asserts executable llvm-mc /home/baldrick/osuosl/slave/llvm-x86_64/llvm/tools/llvm-mc/Debug+Asserts/llvm-mc.o: In function

Hi, On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: > On 7/3/2012 5:01 AM, Duncan Sands wrote: >> Hi, >> >>> (4) llc -march=hexagon test.ll -o test.s >>> >>> '' is not a recognized processor for this target (ignoring processor) >>> 0 llc 0x08c2512b &g...

Hey folks, We are having some difficulty with how we have been representing our predicate registers, and wanted some advice from the list. First, we had been representing our predicate registers as 1 bit (i1). The truth, however, is that they are 8 bits. The reason for this is that they serve as predicates for conditional execution of instructions, branch condition codes, and also as

Hi Sebastian, On 19/07/12 05:57, Sebastian Pop wrote: > On Tue, Jul 3, 2012 at 9:27 PM, Sebastian Pop <spop at codeaurora.org> wrote: >> Hi, >> >> On Tue, Jul 3, 2012 at 9:48 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >>> On 7/3/2012 5:01 AM, Duncan Sands wrote: >>>> Hi, >>>> >>>>> (4) llc -march=hexagon test.ll -o test.s >>>>> >>>>> '' is not a recognized processor for this target (ignor...

On 7/3/2012 5:01 AM, Duncan Sands wrote: > Hi, > >> (4) llc -march=hexagon test.ll -o test.s >> >> '' is not a recognized processor for this target (ignoring processor) >> 0 llc 0x08c2512b >> Stack dump: >> 0. Program arguments: llc -march=hexagon test.ll -o test.s >> 1. Running pass 'Function Pass Manager' on module

...39;re right. I can have use RowFields for that purpose. Thanks, Jyotsna -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, August 20, 2012 3:42 PM To: Jyotsna Verma Cc: 'Tony Linthicum'; llvmdev at cs.uiuc.edu Subject: Re: TableGen related question for the Hexagon backend On Aug 20, 2012, at 1:32 PM, "Jyotsna Verma" <jverma at codeaurora.org> wrote: > In the Hexagon backend, a predicated instruction can translate into > another form called 'predi...

Hi Eli, On Thu, Mar 1, 2012 at 2:21 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote: >> Hey folks, >> >> We are having some difficulty with how we have been representing our >> predicate registers, and wanted some advice from the list.  First, we >> had been representing our predicate registers as 1 bit (i1).  Th...